Toshiba TLCS-900/H1 Series Manual page 42

The operation of each of the different Halt Modes is described in Table 3.4.4.
HALT Mode
SYSCR2 <HALTM1:0>
CPU, MAC
I/O ports
TMRA, TMRB
SIO,SBI
A/D converter
Block
WDT
2
I S, SDRAMC,
Interrupt controller,
SPIC, DMAC, NDFC,
USB
RTC, MLD
(2) How to release the Halt mode
These HALT states can be released by resetting or requesting an interrupt. The halt
release sources are determined by the combination of the states of the interrupt mask
register <IFF2:0> and the halt modes. The details for releasing the HALT status are
shown in Table 3.4.5.
• Release by interrupt requesting
The HALT mode release method depends on the status of the enabled interrupt.
When the interrupt request level set before executing the "HALT" instruction exceeds
the value of the interrupt mask register, the interrupt is processed depending on its
status after the HALT mode is released, and the CPU status executing the instruction
that follows the HALT instruction. When the interrupt request level set before
executing the HALT instruction is less than the value of the interrupt mask register,
HALT mode release is not executed.(in non-maskable interrupts, interrupt processing
is processed after releasing the halt mode regardless of the value of the mask register.)
However only for NMI, INT0 to INT5, INT6, INT7 (asynchronous interrupt),
INTKEY,INTRTC, INTALM interrupts, even if the interrupt request level set before
executing the "HALT" instruction is less than the value of the interrupt mask register,
HALT mode release is executed. In this case, the interrupt is processed, and the CPU
starts executing the instruction following the HALT instruction, but the interrupt
request flag is held at "1".
•
Release by resetting
Release of all halt statuses is executed by resetting.
When the STOP mode is released by RESET, it is necessary to allow enough
resetting time for operation of the oscillator to stabilize.
When releasing the halt mode by resetting, the internal RAM data keeps the state
before the "HALT" instruction is executed. However the other settings contents are
initialized. (Releasing due to interrupts keeps the state before the "HALT" instruction
is executed.)
Table 3.4.4 I/O operation during Halt Modes
IDLE2
11
Depends on PxDR register setting
Available to select
Operation block
Operate
92CF30-40
IDLE1
10
Stop
Stop
Operate
TMP92CF30
STOP
01
2009-06-12