Toshiba TLCS-900/H1 Series Manual page 479

3.18.3 Description of Operation
(1) Settings the transfer clock generator and Word Select signal
In the I
generated using the system clock (f
a prescaler and a dedicated clock generator to set the transfer clock and sampling
frequency.
The counters are started by setting I2S0CTL<CNTE0> to "1" and are stopped and
cleared by setting <CNTE0> to "0".
A) Clock generator
•
clock selected by I2S0CTL<CLKS0>.
•
I2S0CKO signal.
B) Word Select
•
whether left data or right data is being transmitted in the I
signal is clocked out in synchronization with the data transfer clock. In only
channel 0, this signal can be used as an AD conversion trigger signal for the
ADC. How valid data is to be output in relation to the WS signal can be
specified as I
interrupt request can be output to the ADC on the rising edge of the WS signal.
(This is controlled by the ADC's control register.)
(2) Data format
This circuit support I
I2S0CTL<DTFMT01:00> register. And support stereo and monaural both, controlled
by I2S0CTL<FSEL0> register.
S unit, the clock frequencies for the I2S0CKO and I2S0WS signals are
2
8-bit counter
This is an 8-bit counter that generates the I2S0CKO signal by dividing the
6-bit counter
This is a 6-bit counter that generates the I2S0WS signal by dividing the
Word Select signal (I2S0WS)
The I2S0WS signal is used to distinguish the position of valid data and
S format, left-justified, or right-justified. In only channel 0, an
2
S format, left justify and right justify format by setting
2
92CF30-477
) as a source clock. The system clock is divided by
SYS
TMP92CF30
S format. This
2
2009-06-12