Toshiba TLCS-900/H1 Series Manual page 478

(h) <EDGE0>
This bit controls relation of phase between I2S0CKO and data.
<EDGE0>="0": the data is changed in the falling of clock, and the data is latched in
the rising edge of clock.
<EDGE0>="1": the data is changed in the rising of clock, and the data is latched the
falling edge of clock.
It is not possible to change phase during data transmission. Before changing the
data format, set <SYSCKE0>="1", <CNTE0>="0" and <TXE0>="0".
(i) <WLVL0>
This bit controls phase of Word Select signal: I2S0WS
I2S0WS signal always out "1" level first. The order of data output changes by
<WLVL0>. Refer the "FIFO buffer and data format" in details.
It is not possible to change phase of Word Select signal during data transmission.
Before changing the data format, set <SYSCKE0>= "1", <CNTE0>= "0" and
<TXE0>="0".
(j) <TEMP0>
This bit is empty flag of output FIFO buffer.
<TEMP0>="1": FIFO buffer is empty, <TEMP0>="0": remain data in FIFO buffer.
This bit is read only. FIFO buffer is cleared by <TXE0>="0"
(k) <FSEL0>
This bit controls sound mode: Stereo / Monaural
<FSEL0>="0": Stereo, <FSEL0>="1": Monaural. Refer the chapter of "Data format"
in details.
It is not possible to change sound mode during data transmission. Before changing
the data format, set <SYSCKE0>="1", <CNTE0>="0" and <TXE0>="0".
(l) <CLKS0>
This bit controls source clock to I
<CLKS0>="0": f
In case of using f
time. In details, refer the chapter of PLL, please.
(m) <CK07:00>
These bits are set counter value of clock generator. [I2S0CK]
It is not possible to change these counter value during data transmission. Before
changing the counter value, set <SYSCKE0>="1", <CNTE0>="0" and <TXE0>="0".
(n) <WS05:00>
These bits are set counter value of clock generator. [I2S0WS]
It is not possible to change these counter value during data transmission. Before
changing the counter value, set <SYSCKE0>="1", <CNTE0>="0" and <TXE0>="0".
S circuit: f
2
is supplied, <CLKS0>="1": f
SYS
, before set f
PLL PLL
92CF30-476
/ f .
SYS PLL
is supplied.
PLL
clock, please take care set-up time: Lock-Up
TMP92CF30
2009-06-12