Toshiba TLCS-900/H1 Series Manual page 168

(c) External bus read cycle (1 wait state + TAC: 1×1/f
External bus write cycle (1 wait state + TAC: 1×1/f
SDCLK
(80 MHz)
CSn
A23 to A0
RD SRxxB
D31 to D0
SRWR , SRxxB
WRxx
D31 to D0
Note: Above diagram shows case of 32-bit bus access.
(d) External bus read/write cycle (4 wait states +
SDCLK
(80 MHz)
CSn
A23 to A0
RD SRxxB
D31 to D0
SRWR , SRxxB
WRxx
D31 to D0
WAIT
Note: Above diagram shows case of 32-bit bus access.
T1 T2 T3
TAC
TCRS
TCWS
TCWS
T1 T2 T3
92CF30-166
+ TCRS: 1.5×1/f
SYS
+ TCWS/H: 1.5×1/f
SYS
T4 T5
TCRH
Input
TCWH
TCWH
Output
pin input mode)
WAIT
T4 T5
Output
Sampling
TMP92CF30
SYS
+ TCRH: 1×1/ f )
SYS
)
SYS
T6
TAC
Read
Write
T6
Read
Input
Write
2009-06-15