Toshiba TLCS-900/H1 Series Manual page 244

(3) Timer registers (TA0REG and TA1REG)
These are 8-bit registers, which can be used to set a time interval. When the
value set in the timer register TA0REG or TA1REG matches the value in the
corresponding up counter, the comparator match detect signal goes active. If the
value set in the timer register is 00H, the signal goes active when the up counter
overflows.
TA0REG has a double buffer structure, making a pair with the register buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG's
double buffer structure is enabled or disabled. It is disabled if <TA0RDE> = "0" and
enabled if <TA0RDE> = "1".
When the double buffer is enabled, data is transferred from the register buffer to
the timer register when a 2
PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode.
(When using the double buffer, method of renewing timer register is only
overflow in PWM mode or frequency agreement in PPG mode.)
A reset initializes <TA0RDE> to "0", disabling the double buffer. To use the
double buffer, write data to the timer register, set <TA0RDE> to "1", and write the
following data to the register buffer. Figure 3.12.5 shows the configuration of
TA0REG.
Timer registers 0 (TA0REG)
Shift trigger
Register buffer 0
Write
Internal data bus
Figure 3.12.5 Configuration of timer register (TA0REG)
Note: The same memory address is allocated to the timer register and the register buffer 0. When <TA0RDE> = "0",
the same value is written to the register buffer 0 and the timer register; when <TA0RDE> = "1", only the register
buffer 0 is written to.
overflow occurs in PWM mode, or at the start of the
n
B
Selector
S A
TA01RUN<TA0RDE>
92CF30-242
TMP92CF30
Matching detection PPG cycle
n
2 overflow of PWM
Write to TA0REG
2009-06-12