Toshiba TLCS-900/H1 Series Manual page 553

Write cycle
No. Parameter
D0 to D31 valid
16-1
→
xx rising at 0 waits
WR
D0 to D31 valid
16-2
→
xx rising at 2 waits/4 waits
WR
17-1 xx low width at 0 waits
WR
17-2 xx low width at 2 waits/4 waits
WR
18 A0 to A23 valid →
WR
xx falling → SDCLK rising
19
WR
xx rising → A0 to A23 hold
20
WR
xx rising → D0 to D31 hold
21
WR
rising → D0 to D31 output
22
RD
23-1 Write width for SRAM at 0 waits
23-2 Write width for SRAM at 2 waits/4 waits
Data byte control ~ end of write
24-1
for SRAM at 0 waits
Data byte control ~ end of write
24-2
for SRAM at 2 waits/4 waits
25 Address setup time for SRAM
26 Write recovery time for SRAM
27-1 Data setup time for SRAM at 0 waits
Data setup time for SRAM
27-2
at 2 waits/4 waits
28 Data hold time for SRAM
AC measuring condition
• Data_bus, Address_bus, various function control signal capacitance C
Symbol
t
DW
t
DW2
t
DW4
t
WW
t
WW2
t
WW4
falling t
AW
t
WK
t
WA
t
WD
t
RDO
t
SWP
t
SWP2
t
SWP4
t
SBW
t
SBW2
t
SBW4
t
SAS
t
SWR
t
SDS
t
SDS2
t
SDS4
t
SDH
92CF30-551
Variable
80MHz 60MHz Unit
Min Max
1.0T − 6.0
3.0T − 6.0
31.5
5.0T − 6.0
56.5
1.0T − 4.0
3.0T − 4 .0
33.5
5.0T − 4.0
58.5
0.5T − 5.0
1.25
0.5T − 5.0
1.25
0.5T − 5.0
1.25
0.5T − 5.0
1.25
0.5T − 1.0
5.25
1.0T − 4.0
3.0T − 4 .0
33.5
5.0T − 4.0
58.5
1.0T − 4.0
3.0T − 4.0
33.5
5.0T − 4.0
58.5
0.5T − 5.0
1.25
0.5T − 5.0
1.25
1.0T − 6.0
3.0T − 6.0
31.5
5.0T − 6.0
56.5
0.5T − 5.0
1.25
TMP92CF30
6.5 10.6
43.8
77.0
8.5 12.6
45.8
79.0
3.3
3.3
3.3
3.3
7.3
ns
8.5 12.6
45.8
79.0
8.5 12.6
45.8
79.0
3.3
3.3
6.5 10.6
43.8
77.0
3.3
= 50 pF
L
2009-06-12