Toshiba TLCS-900/H1 Series Manual page 359

3.16.3.2 EPx_FIFO Register (x: 0 to 3)
defined by the endpoint descriptor for each endpoint automatically. By this means,
each endpoint is automatically set to each voluntary direction.
Endpoint0 bit Symbol EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0
(0780H)
Read/Write
Undefined
Reset State
Endpoint1 bit Symbol EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DATA1 EP1_DATA0
(0781H)
Read/Write
Reset State Undefined
Endpoint2 bit Symbol EP2_DATA7 EP2_DATA6 EP2_DATA5 EP2_DATA4 EP2_DATA3 EP2_DATA2 EP2_DATA1 EP2_DATA0
(0782H)
Read/Write
Reset State Undefined
Endpoint3 bit Symbol EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0
(0783H)
Read/Write
Reset State Undefined
Note: Read or write to these window registers using 1-byte load instructions only, since each register has only a 1-
byte address. Do not use load instructions of 2 bytes or 4 bytes.
8-byte registers:
wLength_L and wLength_H. These are updated whenever a new SETUP token is
received from the host.
the new device request has been received.
request received.
the
STANDARD_REQUEST_FLAG and REQUEST_FLAG.
This register is prepared for each endpoint independently.
This is the window register from or to FIFO RAM.
In the auto bus enumeration, the request controller in UDC sets the mode, which is
7 6
R/W R/W R/W
Undefined Undefined
7 6
R/W R/W R/W
Undefined Undefined
7 6
R/W R/W R/W
Undefined Undefined
7 6
R/W R/W R/W
Undefined Undefined
The device request that is received from the USB host is stored in the to following
bmRequestType, bRequest,
When the UDC receives without error, INT_SETUP interrupt is asserted, meaning
There is also request which is operated automatically by the UDC, depending on the
In that case, the UDC does not assert the INT_SETUP interrupt. Any request which
UDC is currently
5 4
R/W R/W
Undefined Undefined
5 4 3
R/W R/W
Undefined Undefined
5 4 3
R/W R/W
Undefined Undefined
5 4 3
R/W R/W
Undefined Undefined
wValue_L,
operating can
92CF30-357
3 2 1
R/W R/W
Undefined Undefined
2 1
R/W R/W
Undefined Undefined
2 1
R/W R/W
Undefined Undefined
2 1
R/W R/W
Undefined Undefined
wValue_H, wIndex_L,
be checked
TMP92CF30
0
R/W
Undefined
0
R/W
Undefined
0
R/W
Undefined
0
R/W
Undefined
wIndex_H,
by reading
2009-06-12