Chip Select/Wait Controller - Toshiba TMP91C815F Data Book

3.6 Chip Select/Wait Controller

On the TM91C815, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the
number of waits can be set independently for each address area (CS0 to CS3 and others).
The pins /CS0 to /CS3 (which can also function as port pins P60 to P63) are the respective output pins for the
areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding /CS0 to /CS3
pin outputs the Chip Select signal for the specified address area (in ROM or SRAM). However, in order for the
Chip Select signal to be output, the Port 6 Function Register P6FC must be set.
/CS2A to /CS2G and /CSEXA (CS pin except /CS0 to /CS3) are made by MMU.
These pins is /CS pin that area and BANK value is fixed without concern in setting of CS/WAIT controller.
The areas CS0 to CS3 are defined by the values in the Memory Start Address Registers MSAR0 to MSAR3
and the Memory Address Mask Registers MAMR0 to MAMR3.
The Chip Select/Wait Control Registers B0CS to B3CS and BEXCS should be used to specify the Master
Enable/Disable status the data bus width and the number of waits for each address area.
The input pin controlling these states is the bus wait request pin (WAIT).
3.6.1 Specifying an Address Area
The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and
memory address mask registers (MAMR0 to MAMR3).
At each bus cycle, a compare operation is performed to determine if the address on the specified a
location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the
corresponding CS area. In this case, the /CS0 to /CS3 pin outputs the chip select signal and the bus cycle
operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See 3.6.2,
Chip Select/Wait Control Registers.)
91C815-79
TMP91C815