Mode Description - Toshiba TLCS-900/H1 Series Manual

Original cmos 32-bit microcontroller

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Table of Contents

(4) Detailed description of the transfer mode register

Destination INC mode

(DMADn +) ← (DMASn)

If DMACn = 0 then INTTCn

Destination DEC mode

(DMADn -) ← (DMASn)

If DMACn = 0 then INTTCn

Source INC mode

If DMACn = 0 then INTTCn

Source DEC mode

If DMACn = 0 then INTTCn

Source and destination INC mode

(DMADn +) ← (DMASn +)

If DMACn = 0 then INTTCn

Source and destination DEC mode

(DMADn -) ← (DMASn -)

If DMACn = 0 then INTTCn

Destination and fixed mode

(DMADn) ← (DMASn)

If DMACn = 0 then INTTCn

Counter mode

If DMACn = 0 then INTTCn

00 = 1-byte transfer

01 = 2-byte transfer

10 = 4-byte transfer

11 = Reserved

Note 1: n stands for the micro DMA channel number (0 to 7).

DMADn+/DMASn+: Post increment (Register value is incremented after transfer).

DMADn−/DMASn−: Post decrement (Register value is decremented after transfer).

"I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses.

Note 2: The transfer mode register should not be set to any value other than those listed above.

Note 3: The execution state number shows number of best case (1-state memory access).

DMAM0 to DMAM7

Mode Description

Execution Time