Toshiba TLCS-900/H1 Series Manual page 84

3.6.6 Considerations for Using More Than One Bus Master
In the TMP92CF30, the SDRAM controller and DMA controller may act as the bus
master apart from the CPU. Therefore, care must be exercised to enable each of these
functions to operate smoothly.
To facilitate explanation of DMA operation performed by each bus master, the DMA
transfer operation performed by the DMA controller is defined as "HDMA" and the SDRAM
auto refresh operation performed by the SDRAM controller as "ARDMA".
The following explains various cases where two or more bus masters may operate at the
same time.
(1) CPU + HDMA
The DMA controller performs DMA transfer (HDMA) after issuing a bus request to
the CPU and getting a bus acknowledgement. The DMA controller may be active while
the CPU is in HALT mode (IDLE2 mode only), in which case HDMA does not interfere
with the CPU operation. However, if HDMA is started while the CPU is active, the CPU
cannot execute instructions while HDMA is being performed.
Before activating the DMA controller, therefore, it is necessary to estimate the CPU
stop time (defined as "t
interval, and number of channels to be used.
CPU bus stop rate = t
HDMA start interval [s] = HDMA start interrupt period [s]
Note: The HDMA start interval depends on the period of the HDMA start interrupt source. However, it is also possible
to start HDMA by software.
(HDMA) [s] = (Source read time + Destination write time) × Transfer count + α
t
STOP
Memory Type
Read / Write
Read
Write
Note 1: 2-1-1-1 access. Each consecutive address can be accessed in 1 state.
Note 2: The transfer speed varies depending on the combination of source and destination.
a) When the source or destination is internal RAM or internal I/O (SFR), burst access (6-1-1-1 access) is
possible. Only consecutive addresses on the same page can be accessed in 1 state. Additional 4
states are needed at the end of each burst access.
b) When the source or destination is other than internal RAM or internal I/O, 1-word access is used.
Note 3: In the case of 0 waits
I/O Type
Read / Write
Read
Write
(HDMA)") based on the transfer time, transfer start
STOP
(HDMA)[s] / HDMA start interval [s]
STOP
state/byte
External SDRAM
Internal RAM
16-bit bus
Burst 1 / 2
(Note 1)
1 / 4
1 word 6 / 2
Burst 1 / 2
1 / 4
1 word 3 / 2
state/byte
2
I S NANDF
−
2 / 2
2 / 4 2 / 2
92CF30-82
External SRAM
16-bit bus
(Note 2)
(Note 3)
2 / 2
(Note 2)
(Note 2)
(Note 3)
2 / 2
(Note 2)
USB
2 / 2
2 / 2
TMP92CF30
External SRAM
8-bit bus
(Note 3)
2 / 1
(Note 3)
2 / 1
SPI
2 / 4
2 / 4
2009-06-12