Toshiba TLCS-900/H1 Series Manual page 457

(h) SWRST
This bit is used to performs a software reset of the read and write pointers for data
transmission and reception. Stop the data transmission after writing a "0" to the
SPICT<TXE> bit where XEN = "1". Then, write a "1" to the SWRST bit to initialize the
read and write pointers of transmit and receive FIFO buffers.
Writing a "0" to the SPICT<TXE> bit stops data transmission after transmitting the
UNIT data that is currently being transmitted. Then, writing a "1" to the SWRST bit
invalidate the data in the transmit FIFO buffer. Therefore, the data is not output even
if the data transmission is restarted after performing a software reset. Do not write a
"1" to the SWRST bit in the middle of data transmission.
In case of performing data reception, the received data contained in the receive FIFO
buffer becomes invalid.
However, when performing Sequential-mode data reception, data reception
continues even if the data in the receive FIFO buffer becomes invalid. Therefore, stop
data reception by writing a "0" to the SPICT<RXE> bit after receiving the data that is
currently being received. Then, (after confirming there is no UNIT data currently
being received, or ) the receive operation can be stopped completely by writing a "1" to
the SWRST bit after checking no UNIT data in receiving (namely after REND
interrupt or the time to receive 1UNIT).
Do not write a "1" to the SWRST bit during a data reception. Software reset can be
performed in a single-shot operation, which is to write a "1" to the SWRST bit (it is not
required to write a "0" to the SWRST bit). Simultaneous writing of 1s to the XEN and
SWRST bits is also supported.
(i) XEN
This bit enables or disables the internal clock signal. Always set this bit to "1" when
using the SPI controller.
(j) CLKSEL2:0
This bit selects the baud rate. The baud rate is generated using the system clock f
and is programmable as shown below according to the system clock settings.
Data transmission or reception must not be performed while changing the state of
these bits
Note: The SD card of the TMP92CF30 supports a baud rate of up to 20 Mbps. This field should be programmed so
that SPCLK signal does not exceed 20 MHz When setting the baud rates, select less than 20 Mbps according
to the operation speed of CPU (f
Table 3.17.1 Example of Baud Rate
<CLKSEL2:0>
f
SYS
f
SYS
f
SYS
f
SYS
f /16
SYS
f /64
SYS
f /256
SYS
).
SYS
Baud Rate [Mbps]
f SYS = 60 MHz
−
/2
/3
20
/4
15
/8
7.5
3.75
0.9375
0.234375
92CF30-455
f SYS = 80 MHz
−
−
20
10
5
1.25
0.3125
TMP92CF30
SYS
2009-06-12