Toshiba TLCS-900/H1 Series Manual page 282

Original cmos 32-bit microcontroller
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Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0 pin
Main setting
TB0MOD
TB0FFCR
PPFC
INTE56
INTETB0
TB0RUN
Setting in INT6 routine
TB0RG0H/L
TB0RG1H/L
TB0FFCR
INTETB0
Setting in INTTB01 routine
TB0FFCR
INTETB0
X: Don't care, −: No change
When delay time is unnecessary, invert timer flip-flop TB0FF0 when the up counter
value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c)
plus the one –shot pulse width (p) to TB0RG1H/L when the interrupt INT6 occurs. The
TB0FF0 inversion should be enabled when the up counter (UC10) value matched
TB0RG1H/L, and disabled when generating the interrupt INTTB01.
*Clock state
← X
X
1
0
1
0
← X
X
0
0
0
0
1
← X
1
0
0
X
← X
0
0
0
X
0
0
X
X
1
← TB0CP0H/L + 3ms/φT1
← TB0RG0H/L + 2ms/φT1
← X
X
1
1
← X
1
0
0
X
0
← X
X
0
0
← X
0
0
0
X
0
92CF30-280
System clock :
Prescaler clock :
Free-running
Count with φT1
0
1
Load to TB0CP0H/L at the rising edge of TB0IN0
1
0
Clear TB0FF0 to "0"
Disable TB0FF0 inversion
X
Select PP6 as TB0OUT0 pin (port setting)
Enable INT6
0
0
Disable INTTB00, INTTB01
X
1
Start TMRB0
Enable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
0
0
Enable INTTB01
Disable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
0
0
Disable INTTB01
TMP92CF30
f
SYS
f
/4
SYS
2009-06-12

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