Toshiba TLCS-900/H1 Series Manual page 78

(5) HDMAMn (DMA Transfer Mode Setting Register)
The HDMAMn register is used to set the DMA transfer mode.
HDMAM0 to HDMAM5 have the same configuration.
HDMAMn bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note 1: Read-modify-write instructions can be used on all these registers.
Note 2: INC: Post-increment
Dec: Post-decrement
I/O: Fixed memory address
MEM: Memory address to be incremented or decremented
HDMAMn Register
7 6 5
Transfer mode
[7:0]
HDMAM0
(090CH)
HDMAM1
(091CH)
HDMAM2
(092CH)
HDMAM3
(093CH)
HDMAM4
(094CH)
HDMAM5
(095CH)
Figure3.6.6 HDMAMn Register
92CF30-76
4 3
DnM4 DnM3 DnM2
R/W
0 0
DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved (Note 2)
TMP92CF30
2 1 0
DnM1 DnM0
0 0 0
Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved
2009-06-12