Toshiba TLCS-900/H1 Series Manual page 309

Original cmos 32-bit microcontroller

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In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the

data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag

INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received,

the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown

below and INTES0<IRX0C> is set to "1" again, causing an INTRX0 interrupt to be

Setting SC0MOD0<RXE> to "1" initiates SCLK0 output.

(INTRX0 interrupt

SCLK0 output

(<SCLKS> = "0":

rising edge mode)

SCLK0 output

(<SCLKS> = "1":

falling edge mode)

Figure 3.14.22 Receiving operation in I/O Interface Mode (SCLK0 Output Mode)

In SCLK Input Mode the data is shifted to Receiving Buffer 1 when the SCLK input

goes active. The SCLK input goes active when the Receive Interrupt flag INTES0

<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data

is shifted to Receiving Buffer 2 (SC0BUF) following the timing shown below and

INTES0 <IRX0C> is set to "1" again, causing an INTRX0 interrupt to be generated.

(<SCLKS> = "0":

rising edge mode)

(<SCLKS> = "1":

falling edge mode)

(INTRX0 interrupt request)

Figure 3.14.23 Receiving Operation in I/O interface Mode (SCLK0 Input Mode)

Note: The system must be put in the receive-enable state (SC0MOD0<RXE> = "1") before data can be received.