Toshiba TLCS-900/H1 Series Manual page 481

(3) Setting example for the clock generator (8-bit counter/6-bit counter)
The clock generator generates the reference clock for setting the data transfer speed
and sampling frequency.
I2S0C bit Symbol CK07
(180AH)
Read/Write
Reset State
Function
Bit symbol
(180BH)
Read/Write
Reset State
Function
•
<CLKS0>. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
set to within 10 MHz by an appropriate combination of source clock frequency and
divider value.
When f
follows:
Note: It is recommended that the value to be set in I2S0C<CK07:00> be an even number. Although it is possible to set
an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes the High
width of the I2S0CKO signal to become longer by one f
0, the Low width becomes longer than the High width.)
7 6 5
CK06 CK05
0 0 0
Divider value for CK signal (8-bit counter)
15 14 13
WS05
0
Setting the transfer clock I2S0CKO
The transfer clock is generated by dividing the clock selected by I2S0CTL
The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is
8-bit counter set value
00000000
00000001
11111111
= 60 MHz and I2S0C<CK07:00> = 150, the data transfer speed is set as
SYS
I2S0CKO = f /150
SYS
= 60 [MHz]/150 = 400 [kbps]
92CF30-479
4 3 2
CK04 CK03 CK02
R/W
0 0 0
12 11 10
WS04 WS03 WS02
R/W
0 0 0
Divider value for WS signal (6-bit counter)
Divider value
256
1
255
pulse than the Low width. (When <EDGE0> =
or f
SYS PLL
TMP92CF30
1 0
CK01 CK00
0 0
9 8
WS01 WS00
0 0
2009-06-12