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Toshiba TXZ Series Reference Manual

32-bit risc microcontroller advanced encoder input circuit (32-bit)
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TXZ Family
Advanced Encoder Input Circuit(32-bit)
32-bit RISC Microcontroller
TXZ Family
Reference Manual
Advanced Encoder Input Circuit(32-bit)
(A-ENC32-A)
Revision 1.1
2018-10
1 / 55
2018-10-11
Rev. 1.1
© 2018
Toshiba Electronic Devices & Storage Corporation

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  • Page 1 TXZ Family Advanced Encoder Input Circuit(32-bit) 32-bit RISC Microcontroller TXZ Family Reference Manual Advanced Encoder Input Circuit(32-bit) (A-ENC32-A) Revision 1.1 2018-10 1 / 55 2018-10-11 Rev. 1.1 © 2018 Toshiba Electronic Devices & Storage Corporation...

  • Page 2: Table Of Contents

    TXZ Family Advanced Encoder Input Circuit(32-bit) Contents Preface ................................. 5 Related Documents ..............................5 Conventions ................................6 Terms and Abbreviation ............................8 Outlines ................................. 9 Configuration ............................... 10 Function and Operation ..........................11 3.1. Clock Supply ..............................11 3.2. Operation Mode ............................... 11 3.2.1.
  • Page 3 TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.5. [ENxMCMP] (MCMP Comparison Register) ....................... 45 4.2.6. [ENxRATE] (Phase Count Rate Register) ........................46 4.2.7. [ENxSTS] (Status Register) ............................47 4.2.8. [ENxINPCR] (Input Procedure Control Register) ......................48 4.2.9. [ENxSMPDLY] (Sample Delay Register) ........................49 4.2.10.
  • Page 4 TXZ Family Advanced Encoder Input Circuit(32-bit) List of Figures Figure 2.1 Block diagram of Encoder input circuit ................... 10 Figure 3.1 ENCxZ input is valid ([ENxTNCR]<ZEN>=1)................. 12 Figure 3.2 ENCxZ input is invalid ([ENxTNCR]<ZEN>=0)............... 13 Figure 3.3 3-phase decode ([ENxTNCR]<P3EN>=1) ................15 Figure 3.4 2-phase decode ([ENxTNCR]<P3EN>=0) ................

  • Page 5: Preface

    TXZ Family Advanced Encoder Input Circuit(32-bit) Preface Related Documents Document name Exception Clock Control and Operation Mode Product Information Advanced Programmable Motor Control Circuit Programmable Motor Control Circuit Plus 5 / 55 2018-10-11 Rev. 1.1...

  • Page 6: Conventions

    TXZ Family Advanced Encoder Input Circuit(32-bit) Conventions Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly understood from a sentence.
  • Page 7 TXZ Family Advanced Encoder Input Circuit(32-bit) *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** The Flash memory uses the Super Flash® technology Silicon Storage Technology, Inc. under license from Super Flash®...

  • Page 8: Terms And Abbreviation

    TXZ Family Advanced Encoder Input Circuit(32-bit) Terms and Abbreviation The following words are terms or abbreviations mainly used in this Reference Manual. A-PMD Advanced Programmable Motor Control Circuit Analog to Digital Converter BLDC Brush Less DC (Motor) BEMF Back Electro Motive Force Counter Clockwise Clockwise PMD+...

  • Page 9: Outlines

    TXZ Family Advanced Encoder Input Circuit(32-bit) 1. Outlines One unit of Advanced encoder input circuit (32-bit) (hereafter ENC) operates as one channel input circuit (ENCxA/ENCxB/ENCxZ). The list of the functions is shown in the following table. Function Function Operation category An incremental encoder of AB or ABZ type is connected in this mode.

  • Page 10: Configuration

    TXZ Family Advanced Encoder Input Circuit(32-bit) Table 1.1 Signal input pin Encoder Hall sensor Signal name A, B, or Z U, V, or W ENCxA Connection pin ENCxB ENCxZ 2. Configuration Comparison register [ENxINT] [ENxMCMP] [ENxINPCR] [ENxTNCR] [ENxRATE] [ENxINTCR] [ENxRELOAD] Division pulse Division ENCxA...

  • Page 11: Function And Operation

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3. Function and Operation 3.1. Clock Supply When ENC is used, the corresponding clock enable bits should be set to "1" (Clock supply) in fsys supply stop register A ([CGFSYSENA] and [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB] and [CGFSYSMENB]), and fc supply stop register ([CGFCEN]).

  • Page 12: Encoder Mode

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.1. Encoder Mode This mode supports High-speed position sensor (Phase judgment). The incremental encoder (AB and ABZ) should be used. ● Using the rotation edge detection, a division pulse and an interrupt can be generated. ●...

  • Page 13: Figure 3.2 Encxz Input Is Invalid ([Enxtncr]=0)

    TXZ Family Advanced Encoder Input Circuit(32-bit) (2) ENCxZ input is invalid ([ENxTNCR]<ZEN>=0). In the case of [ENxRELOAD]=0x00000380 and [ENxINT]=0x00000002; fsys ENCxA ENCxB ENCxZ Rotation edge pulse ENCLK Internal Z-phase detection signal Z-phase detection <ZDET> Rotation direction CW direction CCW direction Count clear ENCxTIMPLS (2-division)
  • Page 14 TXZ Family Advanced Encoder Input Circuit(32-bit) When [ENxINTCR]<CMPIE>=1 and the counter value becomes [ENxINT] value, INTENCx1 interrupt can be generated. When [ENxINTCR]<MCMPIE>=1 and the counter value becomes [ENxMCMP] value, INTENCx1 interrupt can be generated. When <ZEN>=1, however, the coincidence interrupt is not generated during the interval of [ENxSTS]<ZDET>=0. <ZDET>...

  • Page 15: Sensor Mode

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.2. Sensor Mode The low-speed position sensor (Zero-cross judgment) is supported to use 2-phase hall sensor input and 3-phase hall sensor input. There are three sensor modes, Event count mode, Timer count mode, and Phase count mode. In the timer count mode and the phase count mode, when PMD circuit drives BLDC motor with the pulse signal, the zero cross detection of the induced voltage can be supported using PWM synchronous sampling.

  • Page 16: Figure 3.4 2-Phase Decode ([Enxtncr]=0)

    TXZ Family Advanced Encoder Input Circuit(32-bit) (2) 2-phase decode ([ENxTNCR]<P3EN>=0) In the case of [ENxINT]=0x00000002; fsys ENCxA(U) ENCxB(V) ENCxZ(W) Rotation edge pulse ENCLK Rotation direction CW direction CCW direction Count clear ENCxTIMPLS (2-division) 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000...

  • Page 17: Timer Count

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.2.2. Timer Count (1) 3-phase decode ([ENxTNCR]<P3EN>=1) In the case of [ENxINT]=0x00000002; fsys ENCxA(U) ENCxB(V) ENCxZ(W) Rotation edge pulse ENCLK Rotation direction CW direction CCW direction ENCxTIMPLS (2-divison) Counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 2 3 0 1 2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 Capture register 0(ini) Interrupt INTENCx0...
  • Page 18 TXZ Family Advanced Encoder Input Circuit(32-bit) The counter always increments. It is cleared to "0" by ENCLK. When [ENxTNCR]<ENCLR> is set to "1", the counter is cleared to "0". The counter value is captured by ENCLK. The captured value can be read through [ENxCNT] register. When [ENxTNCR]<SFTCAP>...

  • Page 19: Phase Count

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.2.3. Phase Count (1) 3-phase decode ([ENxTNCR]<P3EN>=1) [ENxRATE]<RATE> Set clock ENCxA(U) ENCxB(V) ENCxZ(W) Rotation edge pulse ENCLK Rotation direction CW direction CCW direction ENCxTIMPLS (2-division) Counter 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 2 3 0 1 2 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 Capture Register 0 (ini) Interrupt INTENCx0...
  • Page 20 TXZ Family Advanced Encoder Input Circuit(32-bit) "0x00000000", the counter value is set to [ENxRELOAD] value. When <ENCLR> is set to "1", the counter is cleared to "0x00000000". When <TOVMD>=1 is set, the counter stops at the value in [ENxRELOAD]. The counter value is captured by ENCLK. The captured value can be read through [ENxCNT] register. When <SFTCAP>...

  • Page 21: Timer Mode

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.3. Timer Mode This circuit can be used as a general purpose 32-bit timer. ● 32-bit up-counter (fsys clock for counting) ● Counter clear control (Software clear, Comparison match clear, and External trigger) ● A match interrupt is generated by the comparison function.
  • Page 22 TXZ Family Advanced Encoder Input Circuit(32-bit) When <ZEN>=1, ENCxZ input is used as an external trigger. When <ZEN>=0, no external triggers are used. The counter always increments. When [ENxTNCR]<ENCLR> is set to "1", the counter is cleared to "0". When <ZEN>=1 and [ENxTNCR]<ZESEL>=01, the counter is cleared to "0" by ENCxZ rising edge. And when <ZESEL>=10, it cleared by ENCxZ falling edge, and, when <ZESEL>=11, cleared by both edges.

  • Page 23: Phase Counter Mode

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.4. Phase Counter Mode 3.2.4.1. Phase Measurement The counter is 32-bit one which is controlled by any frequency clock. ● Up- and down-count are available. ● Comparison function is available and a match interrupt can be generated. ●...
  • Page 24 TXZ Family Advanced Encoder Input Circuit(32-bit) When <ZEN>=1, ENCxZ input is used as an external trigger. When <ZEN>=0, no external triggers are used. Using [ENxTNCR]<UDMD> setting and [ENxRATE] register setting, the up-count and the down-count of the counter are controlled with any frequency clock. At up-count, when the counter value becomes [ENxRELOAD] value, the counter is cleared to "0".

  • Page 25: Phase Difference Measurement

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.2.4.2. Phase Difference Measurement The phase difference can be measured in the phase counter mode with setting <P3EN>=<ZEN>=1. The up- and down-counter is controlled by the output of the general purpose timer (ENCxPSGI) and ENCxZ input.

  • Page 26: Function Outline Of Each Circuit

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3. Function Outline of Each Circuit 3.3.1. Input Circuit [ENxCLKCR]<SPLCKS> fsys Divider 1, 1/2, 1/4, and 1/8 [ENxSMPDLY]<SMPDLY> Sample clock PWM signal from PMD [ENxINPCR]<SYNCSPLMD> Sampling ENCxPWMON control [ENxINPCR]<SYNCSPLEN> [ENxINPCR]<SYNCNCZEN> Sampling Sampling [ENxINPCR]<NCT> signal enable Noise ENCxA...

  • Page 27: Sample Clock

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.1.1. Sample Clock The sample clock can be selected from among fsys, fsys/2, fsys/4, and fsys/8 by [ENxCLKCR]<SPLCKS>. 3.3.1.2. Sampling Mode (1) Continuous sampling ([ENxINPCR]<SYNCSPLEN>=0) The input signals are sampled by the sampling clock which is selected by [ENxCLKCR]<SPLCKS>. (2) PWM synchronous sampling ([ENxINPCR]<SYNCSPLEN>=1) The sampling is done at the timing synchronous with PWM signal (ENCxPWMON) from PMD.

  • Page 28: Noise Cancellation

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.1.3. Noise Cancellation (1) Continuous sampling ([ENxINPCR]<SYNCSPLEN>=0) The noise cancellation time should be set to [ENxINPCR]<NCT>. The real noise cancellation time is calculated by the following formula. Noise cancellation time: <NCT> × Sample clock cycle Note: When <NCT>...

  • Page 29: Figure 3.18 Noise Cancellation (Pwm-On Interval Sampling And Pwm-Off Interval Clear: =4)

    TXZ Family Advanced Encoder Input Circuit(32-bit) ENCxA input Sampling signal Sampling enable Sampled input signal Edge clear Edge clear Off interval clear Off interval clear Off interval clear Noise filter Counter Figure 3.18 Noise cancellation (PWM-On interval sampling and PWM-Off interval clear: <NCT>=4) 29 / 55 2018-10-11...

  • Page 30: Decoder

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.2. Decoder Abnormal input Skip detection detection [ENxSTS] [ENxTNCR] [ENxSTS] <SKPDT> <P3EN> <SDTEN> <INERR> [ENxTNCR] <DECMD> Sample status Detection status Skip and [ENxINPMON] [ENxINPMON] Edge detection Abnormal Reversed skip <SPLMONA> <DETMONA> error input CW direction skip <SPLMONB>...

  • Page 31: Rotation Edge Detection And Direction Signal Generation

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.2.1. Rotation Edge Detection and Direction Signal Generation (1) 2-phase decode ([ENxTNCR]<P3EN>=0) The encoder mode and the sensor mode (2-phase input) are supported. A change of input patterns (a rotation edge) among 4 patterns is detected in 2-phase decode. CW direction input: The rotation edges of (1)(2), (2)(3), (3)(4), and (4)(1) are detected.

  • Page 32: Z Judgment Circuit

    TXZ Family Advanced Encoder Input Circuit(32-bit) (2) 3-phase decode ([ENxTNCR]<P3EN>=1) The sensor mode (3-phase input) is supported. A change of input patterns (a rotation edge) among 6 patterns is detected in 3-phase decode. CW direction input: The rotation edges of (1)(2), (2)(3), (3)(4), (4)(5), (5)(6), and (6)(1) are detected.

  • Page 33: Skip Judgment And Abnormal Input Judgment

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.2.3. Skip Judgment and Abnormal Input Judgment (1) Skip judgment This function is valid when [ENxTNCR]<SDTEN>=1. When a skip is detected, <SKPDT> is set to "1". ● Skip detection in 2-phase decode ([ENxTNCR]<P3EN>=0) Reversed skip detection: (1)(3), (2)(4), (3)(1), and (4)(2) ●...

  • Page 34: Buffer Update Control

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.2.5. Buffer Update Control When the selection of the decoder detection direction ([ENxTNCR]<DECMD>) is set to "00", the buffer is always valid. The rotation edge judgment and the skip judgment are done by the change of the input signals. When <DECMD>...

  • Page 35: Counter

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.3. Counter The counter circuit consists of a clock generator, a counter, a comparison function, a capture function, and others. The used internal circuits depend on an operation mode. 3.3.3.1. Encoder Mode and Sensor Mode (Event Count) [ENxINTCR] Commutation trigger <MCMPIE>...

  • Page 36: Sensor Mode (Timer Count) And Timer Mode

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.3.2. Sensor Mode (Timer Count) and Timer Mode [ENxTNCR] [ENxINTCR] Commutation trigger <MCMPMD> <MCMPIE> CTRGO To PMD [ENxMCMP] Magnitude MCMP is met comparison [ENxINT] Match 32-bit INT match comparison counter [ENxTNCR] <CMPSEL> fsys Match Clear RELOAD match [ENxRELOAD]...

  • Page 37: Sensor Mode (Phase Count) And Phase Counter Mode

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.3.3. Sensor Mode (Phase Count) and Phase Counter Mode [ENxINTCR] Commutation trigger <MCMPIE> CTRGO PMD へ [ENxMCMP] Match MCMP match comparison 32-bit up- and [ENxINT] Match INT match down-counter [ENxRELOAD] comparison 0 judgment Load Down Match Clear...

  • Page 38: Interrupt Control

    TXZ Family Advanced Encoder Input Circuit(32-bit) 3.3.4. Interrupt Control There are 6 interrupt factors and 2 interrupt outputs. The output of the interrupt of each factor is enabled by Interrupt control register ([ENxINTCR]) individually. The factor generating the current interrupt can be checked in Interrupt flag register ([ENxINTF]).

  • Page 39: Registers

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4. Registers 4.1. List of Registers The control registers and their addresses are shown in the following tables. Base address Peripheral function Channel/Unit TYPE1 TYPE2 TYPE3 0x400F7000 0x400EA000 0x4008A000 0x400EA400 0x4008A400 Advanced Encoder Input Circuit A-ENC32 (32-bit) 0x400EA800...

  • Page 40: Details Of Registers

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2. Details of Registers For a special description in an operation mode is shown separately after [xx mode] ("xx mode" means the corresponding operation mode). 4.2.1. [ENxTNCR] (ENC Control Register) Bit Symbol After Reset Type Description 31:29...
  • Page 41 TXZ Family Advanced Encoder Input Circuit(32-bit) Bit Symbol After Reset Type Description Operation setting at RELOAD match [Sensor mode (Timer count)] 0: Count continues. 1: Count stops. If the counter should be operated from the stop state, the match state should be released by the software clear. [Timer mode, Sensor mode (Phase count), and Phase counter mode (Phase measurement)] 0: Counter is cleared and continues the count.
  • Page 42 TXZ Family Advanced Encoder Input Circuit(32-bit) Bit Symbol After Reset Type Description Operation mode setting 000: Encoder mode 001: Sensor mode (Event counter) 010: Sensor mode (Timer count) 011: Timer mode 100: Reserved. 101: Reserved. 19:17 MODE[2:0] 110: Sensor mode (Phase count) 111: Phase counter mode In Phase counter mode, when <ZEN>=<P3EN>=1, the operation mode becomes "Phase difference measurement ".
  • Page 43 TXZ Family Advanced Encoder Input Circuit(32-bit) Bit Symbol After Reset Type Description [Timer mode and Phase counter mode] This field selects the detection edge in ENCxZ input enable (<ZEN>=1). (ENCxZ input/ENCxPSGI input) 00: Reserved. 01: Rising edge detection 10: Falling edge detection ZESEL[1:0] 11: Both edge detection The detection target is ENCxPSGI input in the phase difference...

  • Page 44: Enxreload] (Reload Comparison Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.2. [ENxRELOAD] (RELOAD Comparison Register) Bit Symbol After Reset Type Description [Encoder mode] The maximum value of the counter is set. (Input pulse count per rotation) x 4 – 1 is set. [Sensor mode (Phase count) and Phase counter mode(Phase measurement)] The maximum value of the counter (the count region per rotation) is set.

  • Page 45: Enxcnt] (Counter Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.4. [ENxCNT] (Counter Register) Bit Symbol After Reset Type Description [Encoder mode and Sensor mode (Event count)] The counter value of the rotation edge pulses can be read. [Sensor mode (Timer count and Phase count)] The captured value of the internal counter by the rotation edge pulse (ENCLK) can be read.

  • Page 46: Enxrate] (Phase Count Rate Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.6. [ENxRATE] (Phase Count Rate Register) Bit Symbol After Reset Type Description 31:16 Read as "0". [Sensor mode (Phase count) and Phase counter mode] The count frequency of the counter is set. Generated clock frequency: fsys × <RATE> /2 By [ENxTNCR]<UDMD>...

  • Page 47: Enxsts] (Status Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.7. [ENxSTS] (Status Register) Bit Symbol After Reset Type Description 31:15 Read as "0". [Sensor mode (Timer count and Phase count)] The reversed <UD> flag at both direction detection (Note1) (Note2) 0: - REVERR 1: Reversed <UD>...

  • Page 48: Enxinpcr] (Input Procedure Control Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.8. [ENxINPCR] (Input Procedure Control Register) Bit Symbol After Reset Type Description 31:15 Read as "0". Noise cancellation time (Note1) Setting range: 0 to 127 (0x00 to 0x7F) Cancellation time: Setting value × Sample clock cycle (by [ENxCLKCR]<SPLCKS>...

  • Page 49: Enxsmpdly] (Sample Delay Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.9. [ENxSMPDLY] (Sample Delay Register) Bit Symbol After Reset Type Description 31:8 Read as "0". Sampling disable interval Setting range: 0 to 255 (0x00 to 0xFF) Disable interval: <SMPDLY> value x Sampling cycle (by [ENxCLKCR]<SPLCKS> setting) SMPDLY[7:0] 0x00 This field sets the sampling disable interval after PWM is On in the...

  • Page 50: Enxclkcr] (Sample Clock Control Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.11. [ENxCLKCR] (Sample Clock Control Register) Bit Symbol After Reset Type Description 31:2 Read as "0". Sampling frequency 00: fsys 01: fsys/2 10: fsys/4 11: fsys/8 SPLCKS[1:0] The sampling frequency is selected for ENCxA, ENCxB, and ENCxZ inputs.

  • Page 51: Enxintcr] (Interrupt Control Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.12. [ENxINTCR] (Interrupt Control Register) Bit Symbol After Reset Type Description 31:6 Read as "0". MCMP met interrupt enable 0: Disable MCMPIE 1: Enable When "1" is set to this bit and MCMP is met, INTENCx1 is generated.

  • Page 52: Enxintf] (Interrupt Flag Register)

    TXZ Family Advanced Encoder Input Circuit(32-bit) 4.2.13. [ENxINTF] (Interrupt Flag Register) Bit Symbol After Reset Type Description 31:6 Read as "0". MCMP comparison met flag MCMPF 0: Not generated. 1: Generated. RELOAD match flag 0: Not generated RLDCPF 1: Generated In Encoder mode and Sensor mode (Event count), this bit is not set.

  • Page 53: Precaution For Usage

    TXZ Family Advanced Encoder Input Circuit(32-bit) 5. Precaution for Usage ● Before the clock supply is shut down, it should be checked that ENC has stopped. And, before the operation mode is changed to the stop mode, it should be checked that ENC has stopped. 53 / 55 2018-10-11 Rev.

  • Page 54: Revision History

    TXZ Family Advanced Encoder Input Circuit(32-bit) 6. Revision History Table 6.1 Revision history Revision Date Description 2018-06-18 First release - Conventions Modified explanation of trademark - 2. Configuration Figure 2.1: "Encoder input circuit""ENC" incremental encoder input" - 3.2.1. Encoder Mode " incremental encoder"...

  • Page 55: Restrictions On Product Use

    Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"...

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