Toshiba TLCS-900/H1 Series Manual page 163

(4) Wait control
The external bus cycle completes in two states at minimum (25 ns at f
without inserting a wait state.
Setting up the BnCSL<BnWW3:BnWW0> bits specifies the number of wait states to be
inserted in a write cycle, and setting the BnCSL<BnWR3:BnWR0> bits specifies the
number of wait states to be inserted in a read cycle. The external bus cycle can be
programmed as follows;
BnCSL<BnWW>/<BnWR>
<BnWW3> <BnWW2>
<BnWR3> <BnWR2>
0 0
0 0
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
0 1
0 0
Other than the above
Note 1: For SDRAM, the above settings are not effective. Refer to Section 3.11, SDRAM controller.
Note 2: For NAND flash memory, the above settings are not effective.
(a) Fixed wait-state mode
The bus cycle is completed in the specified number of states. The number of states
can be selected from 2 (0 wait state) through 12 (10 wait states), 14 (12 wait states), 18
(16 wait states) and 22 (20 wait states).
(b) pin input mode
WAIT
In this mode, the
while the
WAIT
states. The bus cycle is completed if the
edge of SDCLK in the sixth state. The bus cycle is extended as long as the
remains active after sixth state.
<BnWW1> <BnWW0>
<BnWR1> <BnWR0>
0 1
1 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
1 1
signal is sampled. A wait state is continued to be inserted
WAIT
signal is sampled active. The minimum bus cycle in this mode is six
92CF30-161
Number of Wait States
2 states (0 wait state), fixed wait-state mode
3 states (1 wait state), fixed wait-state mode (Default)
4 states (2 wait states), fixed wait-state mode
5 states (3 wait states), fixed wait-state mode
6 states (4 wait states), fixed wait-state mode
7 states (5 wait states), fixed wait-state mode
8 states (6 wait states), fixed wait-state mode
9 states (7 wait states), fixed wait-state mode
10 states (8 wait states), fixed wait-state mode
11 states (9 wait states), fixed wait-state mode
12 states (10 wait states), fixed wait-state mode
14 states (12 wait states), fixed wait-state mode
18 states (16 wait states), fixed wait-state mode
22 states (20 wait states), fixed wait-state mode
6 states + pin input mode
WAIT
Reserved
signal is sampled High at the rising
WAIT
TMP92CF30
= 80 MHz)
SYS
signal
WAIT
2009-06-15