Toshiba TLCS-900/H1 Series Manual page 324

Original cmos 32-bit microcontroller
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SBISR
Bit symbol
(1243H)
Read/Write
Reset State
A read-
Function
Master/ Slave
modify-write
status
operation
monitor
cannot be
0:Slave
performed
1:Master
Note1: Writing in this register functions as SBICR2.
Note2: The initialdata SBISR<PIN> is "1" if SBI operation is enable (SBICR0<SBIEN>="1"). If SBI operation is disable
(SBICR0<SBIEN>="0"), the initialdata of SBISR<PIN> is "0".
Serial Bus Interface Status Register
7
6
5
MST
TRX
BB
0
0
0
2
Transmitter/
I
C bus status
Receiver
monitor
status
0:Free
monitor
1:Busy
0:Receiver
1:Tranmitter
Figure 3.15.6 Registers for the I
4
3
PIN
AL
R
1
0
INTSBI
Arbitration
interrupt
lost detection
request
monitor
0: −
monitor
0: Interrupt
1: Detected
requested
1: Interrupt
canceled
2
C bus mode
92CF30-322
TMP92CF30
2
1
AAS
AD0
0
0
Slave
GENERAL
Last
address
CALL
received bit
match
detection
monitor
detection
monitor
0: 0
monitor
0:Undetected
1: 1
0:Undetected
1: Detected
1: Detected
Last received bit monitor
0
Last received bit was 0
1
Last received bit was 1
GENERAL CALL detection monitor
0
Undetected
1
GENERAL CALL detected
Slave address match detection monitor
0
Slave address don't match or Undetected
Slave address match or GENERAL CALL
1
detected
Arbitration lost detection monitor
0
1
Arbitration lost
0
LRB
0
2009-06-12

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