Toshiba TLCS-900/H1 Series Manual page 41

3.4.6 Standby controller
(1) HALT Modes and Port Drive register
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1:0> register
and each pin-status is set according to the PxDR register, as shown below.
7
PxDR bit symbol Px7D
(xxxxH)
Read/Write
System
1
Reset State
Hot Reset
−
State
Function
(Purpose and using)
• This register is used to set each pin-status at stand-by mode.
• All ports have this registers of the format shown above ("x" indicates the port-name.)
• For each register, refer to 3.7 Function of Ports.
• Before "HALT" instruction is executed, set each register pin-status. They will be
effective after the CPU has executed the "HALT" instruction.
• This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP).
The Output/Input-buffer control table is shown below.
Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE.
Note2: "n" in PxnD denotes the bit number of PORTx.
The subsequent actions performed in each mode are as follows:
6 5
Px6D Px5D
1 1
− −
Output/Input buffer drive-register for standby-mode
OE PxnD Output buffer
0 0 OFF
0 1 OFF
1 0 OFF
1 1 ON
a. IDLE2: Only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by
setting the following register.
Table 3.4.3 shows the registers setting operation during IDLE2 mode.
Table 3.4.3 SFR setting operation during IDLE2 mode
Internal I/O
TMRA01
TMRA23
TMRA45
TMRA67
TMRB0
TMRB1
SIO0
SBI
A/D converter
WDT
b. IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to
operate.
c. STOP: All internal circuits stop operating.
92CF30-39
4 3 2
Px4D Px3D Px2D
R/W
1 1 1
− − −
Input buffer
OFF
ON
OFF
OFF
SFR
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TA45RUN<I2TA45>
TA67RUN<I2TA67>
TB0RUN<I2TB0>
TB1RUN<I2TB1>
SC0MOD1<I2S0>
SBIBR0<I2SBI>
ADMOD1<I2AD>
WDMOD<I2WDT>
TMP92CF30
1 0
Px1D Px0D
1 1
− −
2009-06-12