Toshiba TLCS-900/H1 Series Manual page 103

P7 bit Symbol
(001CH)
Read/Write
System
Reset State
P7CR bit Symbol
(001EH)
Read/Write
System
Reset State
Function
P7FC bit Symbol
(001FH)
Read/Write
System
Reset State
Function
P7DR bit Symbol
(0087H)
Read/Write
System
Reset State
Function
P73 setting
<
<P73C>
0
<P73F>
0 Input Port Output Port
Reserved EA24Output
1
P76 setting
<P76C>
0
<P76F>
0
Input Port Output Port
1
WAIT Input
Note1: A read-modify-write operation cannot be performed for P7CR, P7FC.
Note2: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch.
Order
------------------------------------------------------
(1)
(2)
(3)
Port 7 register
7 6 5
P76 P75
Data from external port
(Output latch register is
set to "1")
Port 7 Control register
7 6 5
P76C P75C
0 0
Port 7 Function register
7 6 5
P76F P75F
0 0
0:Port
Refer to following table
1: WAIT
Port 7 Drive register
7 6 5
P76D P75D
1 1
Input/Output buffer drive register for standby mode
P72 setting
<
<P72C>
1
<P72F>
0 Input Port
Reserved
1
P75 setting
<P75C>
1
<P75F>
0
Input Port
1
Reserved NDR/
Registser bit2
P7 0
P7FC 1
P7CR 1
Figure 3.7.11 Register for Port 7
4 3
P74 P73
R/W
Data from external port
(Output latch register is
cleared to "0")
4 3
P74C P73C
W
0 0
0: Input 1: Output
4 3
P74F P73F
W
0 0
4 3
P74D P73D
R/W
1 1
P71 setting
0 1
<P71F>
Output Port
Output
NDWE
(at <P72>=0)
Output
WRLU
(at <P72>=1)
P74 setting
0 1
<P74F>
Output Port
Input R/W Output
B
bit1
0
1
1
92CF30-101
TMP92CF30
2 1
P72 P71 P70
Data from external port
(Output latch register is
set to "1")
2 1
P72C P71C
0 0
2 1
P72F P71F P70F
0 0
0:Port 0:Port 0:Port
1: 1: 1:
NDWE RD
at at
NDRE
<P72> = 0 <P71> = 0
at at
WRLU
WRLL
<P72> = 1 <P71> = 1
2 1
P72D P71D P70D
1 1
<P71C>
0 1
0 Input Port Output Port
Reserved
NDRE Output
(at <P71>=0)
1
Output
WRLL
(at <P71>=1)
<P74C>
0 1
0
Input Port Output Port
1
Reserved EA25Output
0
1
0
0
1
0
1
2009-06-12