Toshiba TLCS-900/H1 Series Manual page 323

SBICR2 Bit symbol
(1243H)
Read/Write
A read- Reset State
modify-write
Function Master/Slave
operation
selection
cannot be
0:Slave
performed
1:Master
Note 1: Reading this register functions as SBISR register.
Note 2: Switch a mode to port mode after confirming that the bus is free.
Switch a mode between I
Serial Bus Interface Control Register 2
7 6 5
MST TRX BB
W
0 0 0
Transmitter Start/Stop
/Receiver condition
selection Generation
0:Generate
0:Receiver
stop
1:Transmitter
condition
1:Generate
start
condition
2
C bus mode and port mode after confirming that input signals via port are high-level.
Figure 3.15.5 Registers for the I
Table 3.15.1Resolution of base clock
Clock Gear
<GEAR1:0>
000(fc)
001(fc/2)
010(fc/4)
011(fc/8)
100(fc/16)
4 3
PIN SBIM1
W (Note 1)
1 0
Cancel Serial bus interface
INTSBI operating mode selection
interrupt (Note 2)
request 00: Port mode
0:Don't care 01: Reserved
2
1:Cancel 10: I C Bus mode
interrupt 11: Reserved
request
Serial bus interface operating mode selection (Note2)
00 Port Mode (Serial Bus Interface output disabled)
01 Reserved
2
I C Bus Mode
10
11 Reserved
2
C bus mode
@f
SYS
Base Clock
Resolution
2
f /2 (50ns)
SYS
3
f /2 (0.1μs)
SYS
4
f /2 (0.2μs)
SYS
5
f /2 (0.4μs)
SYS
6
f /2 (0.8μs)
SYS
92CF30-321
TMP92CF30
2 1
SBIM0 SWRST1 SWRST0
W (Note 1)
0 0
Software reset generate
write "10" and "01", then
an internal reset signal is
generated.
= 80MHz
2009-06-12
0
0