Cpu Interface Timing - Epson S1R75801F00A Technical Manual

S1R72803F00A

9.4.4 CPU Interface Timing

9.4.4.1 CPU Read Cycle
P_BCLK
P_A [23:0]
P_CE
X
P_RD_X
P_D[15:0]
P_P30
(Wait input)
t
*1 is formulated according to the earliest signal change (Negate) among P_RD, P_CEx, P_A[23:0]
RDH
Symbol
t Address delay time
AD
t P_CEx delay time (1)
CE1
t P_CEx delay time (2)
CE2
t Wait set-up time
WTS
t Wait hold time
WTH
t Read signal delay time (1)
RDD1
t Read data set-up time
RDS
t Read data hold time
RDH
t Read signal delay time (2)
RDD2
t Read signal pulse width
RDW
t Read address access time (1)
ACC1
t Chip enable access time (1)
CEAC1
t Read signal access time (1)
RDAC1
104
C
1
t
AD
t
CE1
t
RDD (Only C1)
Specification
C (Wait cycle)
W
t
RDW
t
CFAC1
t
ACC1
t
RDA1
t
t
WTS
WTH
Min.
–
–
–
29
0
–
24
0
–
t (0.5+WC)–8
CYC
–
–
–
t
* =40ns when bus clock is 25MHz in X2 mode.
CYC
* WC: Wait cycle signal
EPSON
Cn (Last cycle)
t
AD
t
CE2
t
RDD2
t
RDS
t
RDH
t
t
WTS
WTH
Max.
8
8
8
–
–
8
–
–
8
–
t (1+WC)–20
CYC
t (1+WC)–20
CYC
t (0.5+WC)–20
CYC
*1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns