Watchdog Timer Operations; Watchdog Timer Operation - NEC mPD780024AS Series Preliminary User's Manual

9.4 Watchdog Timer Operations

9.4.1 Watchdog timer operation

When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to
detect any program loops.
The program loop detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer
clock select register (WDCS).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within
the set program loop time interval. The watchdog timer can be cleared and counting is started by setting RUN to
1. If RUN is not set to 1 and the program loop detection time is exceeded, system reset or a non-maskable interrupt
request is generated according to WDTM bit 3 (WDTM3) value.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual program loop detection time may be shorter than the set time by a maximum of
2 8 /f seconds.
X
2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
stopped.
Table 9-4. Watchdog Timer Program Loop Detection Time
Remarks 1. f : Main system clock oscillation frequency
X
2. Figures in parentheses are for operation with f
CHAPTER 9 WATCHDOG TIMER
Program Loop Detection Time
(489 µ s)
12 × 1/f
2
X
(978 µ s)
13 × 1/f
2
X
× 1/f
14
2 (1.96 ms)
X
× 1/f
15
2 (3.91 ms)
X
× 1/f
16
2 (7.82 ms)
X
17 × 1/f
2 (15.6 ms)
X
18 × 1/f
2 (31.3 ms)
X
× 1/f
20
2 (125 ms)
X
= 8.38 MHz.
X
Preliminary User's Manual U16035EJ1V0UM
163