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11.4 Watchdog Timer Operations
11.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated
to detect any inadvertent program loop.
The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to
2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2). Watchdog timer starts by setting bit 7 (RUN) of WDTM
to 1. After the watchdog timer is started, set RUN to 1 within the inadvertent program loop time interval to be set.
The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the
inadvertent program loop detection time is past, system reset or a non-maskable interrupt request is generated
according to the WDTM bit 3 (WDTM3) value.
Watchdog timer can be cleared by setting RUN to 1.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual inadvertent program loop detection time may be shorter than the set time by a
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maximum of 0.5%.
2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
stopped.
Table 11-4. Watchdog Timer Inadvertent Program Loop Detection Time
TCL22
TCL21
TCL20
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Remark
f
: Main system clock oscillation frequency
X
TCL20 to TCL22: Bits 0 to 2 of the timer clock select register 2 (TCL2)
CHAPTER 11 WATCHDOG TIMER
Inadvertent Program Loop Detection Time
× 1/f
12
2
X
× 1/f
2
13
X
× 1/f
2
14
X
× 1/f
15
2
X
× 1/f
2
16
X
× 1/f
17
2
× 1/f
2
18
X
× 1/f
2
20
X
f
= 10.0 MHz
X
409.6 µ s
819.2 µ s
1.64 ms
3.28 ms
6.55 ms
13.1 ms
26.2 ms
104.9 ms
237
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