Rambus Drcg* Clock Routing Recommendation - Intel Pentium 4 Design Manual

Layout Review Checklist
16.3.4

Rambus DRCG* Clock Routing Recommendation

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280
Recommendations
• 3VMRef trace routed from CK00 must be
6 mils wide and separated by 6 mil space
on both sides. A 6 mil wide ground isolation
trace should be placed after 6 mil space.
Max trace length is 8 inches.
• VddiR pin on DRCG* can be connected to
3.3 V plane near the DRCG if the plane
extends near the DRCG. However, if a
3.3 V trace must be used, it should
originate at the clock synthesizer and
routed 6 mil wide with 6 mil spacing with
6 mil wide ground trace following.
• Rclkout and Hclkout from MCH must be
routed to Synclkn and Pclkm on the DRCG.
Signals must be routed together about
12 mils apart with 6 mil wide traces. A 6 mil
wide ground trace located on each side of
the pair. A 6 mil spacing between the
ground trace and Rclkout and Hclkout
signals. Max trace length is 6 inches and
must be length matched within 50 mils
• VddiPD pin on DRCG can be connected to
1.8 V plane near the DRCG if the plane
extends near the DRCG. However, if a
1.8 V trace must be used, it should
originate at the CK00 clock synthesizer and
routed 5 mil wide with 6 mil spacing with
6 mil-wide ground trace.
• Series resistors (39 Ω ) should be mounted
very near CTM/CTM# pins. Parallel
resistors (51 Ω ) should be very near series
resistors.
• CFM pair trace length:
st
 MCH-to-1
RIMM connector 1 inch-6
inches
 RIMM* connector-to-RIMM connector 0.4
inch –1.0 inches.
 2nd RIMM connector-to-Termination 0–2
inches
• CTM pair trace length:
nd
 DRCG-to-2
RIMM connector 0–6 inches
 RIMM connector-to-RIMM* connector
0.4–1.0 inches
 1st RIMM connector-to-MCH 1 inch–6
inches
® ®
Intel Pentium 4 Processor / Intel
Reason/Impact/Documentation
• This recommendation is for microstrip
applications.
• Refer to Section 4.3.1.
• Refer to Section 4.3.1.
• If signals must switch layers then they
should switch layers together.
• Refer to Section 4.3.2.
• Refer to Section 4.3.2.
• Refer to Section 4.3.5.
• Refer to Section 4.3.3.1.
• Refer to Section 4.3.3.1.
®
850 Chipset Family Platform Design Guide
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