Memory Interface Routing - Intel Pentium 4 Design Manual

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Memory Interface Routing

The Direct Rambus channel is a multi-symbol interconnect. Due to the length of the interconnect
and frequency of operation, this bus is designed to allow multiple command and data packets to be
present on a signal wire at any given instant. For example, the driving device can send the next
data out before the previous data has left the bus.
The nature of the multi-symbol interconnect forces many requirements on the bus design and
topology. First and foremost, a drastic reduction in reflected voltage levels is required. The
interconnect transmission lines must be terminated at their characteristic impedance. Otherwise,
the reflected voltage resulting from a mismatch in impedance will degrade signal quality. These
reflections reduce noise margins, timing margins and the maximum operating frequency of the bus.
Second, coupled noise can greatly affect the performance of high-speed interfaces. Just as in
source synchronous designs, odd and even mode propagation velocity change can create skew
between the clock lines, the data lines or command lines which reduces the maximum operating
frequency of the bus. Efforts must be made to significantly decrease crosstalk, as well as the other
sources of skew.
To achieve these bus requirements, all components, including the individual RDRAM devices, are
incorporated into the design to create a uniform bus structure that can support up to 33 devices
(including the MCH) running at 800 MegaTransfers/second (MT/s). The following sections will
document the design guidelines to help ensure a robust Direct Rambus channel design.
Refer http://www.rambus.com/html/direct_docs.html
technology.
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Intel Pentium 4 Processor / Intel
®
850 Chipset Family Platform Design Guide
Memory Interface Routing
for more information regarding RDRAM
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