Intel Pentium 4 Design Manual page 9

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16.2 CK00 Routing Guidelines ................................................................................... 274
16.2.1
16.3 RAMBUS Technology Routing Guidelines ......................................................... 276
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.3.7
16.4 AGP Guidelines .................................................................................................. 282
16.4.1
16.4.2
16.4.3
16.4.4
16.5 8 Bit Hub Interface.............................................................................................. 285
16.5.1
16.6 IDE Interface....................................................................................................... 286
16.7 CNR .................................................................................................................... 286
16.8 Intel
16.9 USB .................................................................................................................... 287
16.10 Intel
16.11 RTC
16.12 LAN* Connect Interface...................................................................................... 288
16.13 Miscellaneous ..................................................................................................... 289
Appendix A: Reference Schematics ....................................................................................................... 291
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Intel Pentium 4 Processor / Intel
CK00 Clocking .................................................................................... 274
RSL Signals ........................................................................................ 276
Ground Isolation.................................................................................. 278
V Layout ......................................................................................... 279
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Rambus DRCG* Clock Routing Recommendation............................. 280
Rambus DRCG* Layout (Clean Power Supply) .................................. 281
Rambus DRCG* (CTM/CTM# Output Network Layout)...................... 282
RAMREF Routing................................................................................ 282
All 1X Signals ...................................................................................... 282
2X/4X Signals...................................................................................... 283
16.4.2.1 AGP Less Than 6 Inches................................................... 283
16.4.2.2 AGP Interface Greater Than 6 Inches and Less Than 7.25
Inches ................................................................................ 284
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Intel MCH AGP Decoupling............................................................... 284
AGP Connector Decoupling ................................................................ 285
Hub Decoupling................................................................................... 285
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AC'97 ........................................................................................................ 286
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ICH2 Decoupling ....................................................................................... 287
............................................................................................................ 288
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850 Chipset Family Platform Design Guide
Introduction
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