Intel Pentium 4 Design Manual page 246

Schematic Review Checklist
Checklist Items
SMI#
STPCLK#
TESTHI
THERMTRIP#
TRDY#
VCCA
VCCIOPLL
VCC_SENSE
VCCVID
V [4:0]
ID
VSSA
V
SS_SENSE
TMS
246
Recommendations
• Connect to ICH2.
• No pull-up required.
• Connect to ICH2.
• No pull-up required.
Refer to Section 5.4.1.11 for more
information.
• Terminate to VCC_CPU via
62 Ω ±5% resistor.
• Voltage translation may be required if
this signal is connected to external
logic.
• Connect to MCH
• Connect with isolated power circuitry
to VCC_CPU.
• Connect with isolated power circuitry
to VCC_CPU.
• Connect to additional glue logic if
used. This signal is an output signal.
• Connect to 1.2V linear regulator
• Connect to VR or VRM. These are
open-drain signals from the processor
and require pull-ups to 3.3 V for
proper operation. Some VR
controllers have internal pull-ups. If
the VR controller used does not have
1 k Ω internal pull-ups, 1 k Ω 5% pull-
ups to 3.3 V should be placed on the
motherboard.
• Connect with isolated power circuitry
to VCC_CPU.
• Connect to additional glue logic if
used. This signal is an output signal.
• Debug port signal. Refer to the latest
revision of the Intel
Processor in the 478-pin Package
Debug Port Design Guide for
information on the connection and
termination of this signal .
® ®
Intel Pentium 4 Processor / Intel
Reason/Impact/Documentation
• Asynch GTL+ input signal
• Refer to Section 5.4.1.2.
• Asynch GTL+ input signal
• Refer to Section 5.4.1.2.
• Tying any of the TESTHI pins together
will prevent the ability to perform
boundary scan testing.
• Refer to processor datasheet .
• Asynch GTL+ output signal
• Refer to Section 5.4.1.1.
• AGTL+ common clock input signal
• Isolated power for internal processor
system bus PLLs.
• Refer to Section 11.4.
• Isolated power for internal processor
system bus PLLs
• Refer to Section 11.4.
• Isolated low impedance connection to
processor core power (VCC)
• Refer to processor datasheet.
• This voltage powers the processor
dynamic VID circuitry.
• Refer to the Intel
Processor in the 478-Pin Package VR
Down Design Guidelines.
• Isolated GND for internal PLLs
• Refer to Section 11.4.
• Isolated low impedance connection to
core VSS.
• Refer to the processor datasheet.
• Debug port signal. Proper termination
® ®
is required for the system to function
Pentium 4
properly.
®
850 Chipset Family Platform Design Guide
R
® ®
Pentium 4