Agp Interface Greater Than 6 Inches And Less Than 7.25 Inches; Intel ® Mch Agp Decoupling - Intel Pentium 4 Design Manual

Layout Review Checklist
16.4.2.2

AGP Interface Greater Than 6 Inches and Less Than 7.25 Inches

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16.4.3 Intel
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284
Recommendations
• Board impedance must be 60 Ω ±10%
• 5 mil trace width 20 mil separation between
data to data
• 5 mil trace width 20 mil separation between
data (and all other signals) to strobes
• 5 mil trace width 20 mil separation between
strobe to strobe
• DATA and C/BE#s need to be length
matched within ±0.125 inches of strobes.
• Strobe pairs must be length matched ±0.1
inches
• Route AD[15:0], C/BE[1:0]#, AD_STB0, and
AD_STB0# together. (Good
recommendation, but not in the AGP
specification)
• Route AD [31:16], C/BE [3:2]#, AD_STB1,
and AD_STB1# together. (Good
recommendation, but not in the AGP
specification)
• Route SBA[7:0], SB_STB, SB_STB#
together. (Good recommendation, but not in
the AGP specification)
• Recommended that all strobes be ground
referenced as well as TRDY#, IRDY#,
GNT#.
• Recommended that ½ the AGP signals are
ground referenced.
• For signals that require pull-up or pull-down
resistors, keep stub less than 0.5 inches for
1X signals and less than 0.01 inches for
2X/4X signals.
• Pour a VSS flood under V
DDQ
MCH AGP Decoupling
Recommendations
• Min of 6 0.01 µF capacitors spread evenly
around the MCH AGP interface.
• Must be within 0.15 inches from package
• Pour a VSS flood under V
DDQ
decouple AGP.
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Intel Pentium 4 Processor / Intel
• Refer to Section 7.1.2.2.
• Refer to Section 7.1.2.2.
• Refer to Section 7.1.2.2.
• Refer to Section 7.1.2.2.
• Refer to Section 7.1.2.2.
• Refer to Section 7.1.2.1.
• Signals to be kept on same layers.
Microstrip-to-microstrip and stripline-to-
stripline.
• Signals to be kept on same layers.
Microstrip-to-microstrip and stripline-to-
stripline.
• Signals to be kept on same layers.
Microstrip-to-microstrip and stripline-to-
stripline.
• Refer to Section 7.1.5.
• Refer to Section 7.1.5.
• This is to minimize signal reflections from
the stub.
• Refer to Section 7.1.9.
plane • Optimizes the mutual inductance between
two planes.
• Refer to Section 7.1.9.
• It is recommended that a low ESL ceramic
capacitor, such as a 0603 body type, X7R
dielectric.
• Refer to Section 7.1.4.
• Refer to Section 7.1.4.
plane to • To help lower inductive path from the
decoupling capacitor.
• Refer to Section 7.1.4.
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850 Chipset Family Platform Design Guide
Reason/Impact
Reason/Impact
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