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Pentium 4
Design manual
Figure 63. Bottom Layer Ctab With Rsl Signal Routed On The Same Layer; Figure 64. Bottom Layer Ctabs Split Across The Top And Bottom Layer To Achieve An - Intel Pentium 4 Design Manual
In the 478-pin package / intel 850 chipset family platform
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Figure 63. Bottom Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 1.35 pF)
The CTAB can be implemented on the multiple layers to minimize routing and space constrains.
Figure 64 issues the use of CTABs on the top and bottom layer for bottom layer RSL and clocking
signals routed between RIMM connectors.
Figure 64. Bottom Layer CTABs Split Across the Top and Bottom Layer to Achieve an Effect
Ceff ~1.35 pF
®
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4 Processor / Intel
®
850 Chipset Family Platform Design Guide
Memory Interface Routing
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