Figure 62. Top Layer Ctab With Rsl Signal Routed On The Same Layer (Ceff = 0.8; Table 24. Copper Tab Area Calculation - Intel Pentium 4 Design Manual

Memory Interface Routing
The following is an example calculation for a board where ε
Note these numbers will vary with differences in prepreg thickness.

Table 24. Copper Tab Area Calculation

Layer
Top
Inner 1
Inner 2
Bottom
1
NOTE: These numbers are based on a six layer stack-up.
Note that more than one copper tab shape may be used as shown in the following figures. The
dimensions are based on copper area over the ground plane. The actual length and width of the
tabs may be different due to routing constraints (e.g., if tab must extend to center of hole or anti-
pad). The following figures show a routing example of tab compensation capacitors. Note, the
capacitor tabs must not interrupt ground floods around the RIMM connector pins, and they must
be connected to avoid discontinuity in the ground plane as shown.
Figure 62. Top Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 0.8 pF)
100
Dielectric Separation
Thickness Between Signal
Traces & Copper
Tab
4.5 6
4.5 6
4.5 6
4.5 6
® ®
Intel Pentium 4 Processor / Intel
is 4.2 and thickness of prepreg is 4.5.
r
Minimum Air Gap
Ground Between
Flood Signal &
GND Flood
10 6
10 6
10 6
10 6
®
850 Chipset Family Platform Design Guide
R
Compensating CTAB
Capacitance in Area in
1
Cplate (pF) sq mils
0.8 ~3460
0.9 ~3900
1.23 ~5300
1.35 ~5800