Figure 103. Cdc_Dn_Enab# Support For Two-Codecs On Motherboard / Two-Codecs On Cnr; Table 34. Signal Descriptions - Intel Pentium 4 Design Manual

R

Figure 103. CDC_DN_ENAB# Support for Two-Codecs on Motherboard / Two-Codecs on CNR

From AC '97
Controller
To General
Purpose Input
To AC '97
Digital
Controller
Circuit Notes
• All CNR designs include resistor R
the intended functionality of the CNR (whether or not it intends to be the primary/controlling
codec).
• Any CNR with two codecs must implement R
100 kΩ pull-up resistor. A CNR with zero codecs must not stuff R
be connected to the same power well as the codec so that it is valid whenever the codec has
power.
• A motherboard with one or more codecs down must implement R
• The CDC_DN_ENAB# signal must be run to a GPI so that the BIOS can sense the state of the
signal. CDC_DN_ENAB# is required to be connected to a GPI; a connection to a GPIO is
strongly recommended for testing purposes.

Table 34. Signal Descriptions

Signal
CDC_DN_ENAB#
AC97_RESET#
SDATA_INn
® ®
Intel Pentium 4 Processor / Intel
Codec A
SDAT A_IN
RESET #
AC97_RESET#
CDC_DN_ENAB#
R
A
10kohm s
SDATA_IN0
SDATA_IN1
. The value of R
B
When low, indicates that the codec on the motherboard is enabled and primary on the
AC97 Interface. When high, indicates that the motherboard codec(s) must be
removed from the AC '97 Interface (held in reset), because the CNR codec(s) will be
the primary device(s) on the AC '97 Interface.
Reset signal from the AC '97 Digital Controller (ICH2).
AC '97 serial data from an AC '97-compliant codec to an AC '97-compliant controller
(i.e., the ICH2).
®
850 Chipset Family Platform Design Guide
Motherboard CNR Board
Codec B
SDATA_IN
R ESET#
Vcc
is either 1 kΩ or 100 kΩ, depending on
B
with value 1 kΩ. If there is one Codec, use a
B
. If implemented, R
B
with a value of 10 kΩ.
A
Description
I/O Controller Hub 2
Codec C
R ESET#
SD AT A_IN
Codec D
R
B
R ESET#
1kohms
SD AT A_IN
CNR Connector
must
B
147