Routing Guidelines For Rambus Rdram* Device Clocks; Ck00 To Rambus Drcg* (Reference Clocks); Figure 18. Vddir And 3Vmref Routing - Intel Pentium 4 Design Manual

Platform Clock Routing Guidelines
4.3 Routing Guidelines for Rambus RDRAM* Device
Clocks
The CK00 clock synthesizer provides two 3.3 V clock reference outputs [3Vmref and 3Vmref#]
for the Direct Rambus* Clock Generator (DRCG* device). Two DRCG devices are required in an
850 chipset dual-Direct RDRAM channel interface. Some clock vendors may also have a DMCG
(Direct Multiple Clock Generator) component that combines the function of two DRCG devices
into one part. These DMCG components may be used as a cost-reduction opportunity with
appropriate validation.
The DRCG device reference clock operates at one-half the processor clock frequency. The
reference clocks are inputs into the DRCG devices and are used to generate the RDRAM device
"Clock to Master" differential pair (CTM, CTM#) clocks on each Direct RDRAM channel.
In addition, the DRCG uses phase information provided by the MCH via the RCLKOUT and
HCLKOUT phase aligning signals.
For an 82850E/PC1066 RDRAM technology platform, the DRCG devices should be 533 MHz
capable.
4.3.1

CK00 to Rambus DRCG* (Reference Clocks)

The 3VMRef clock output must be routed as shown in Figure 18. Note that the VddIR power pin
on the DRCG can be connected directly to 3.3 V near the DRCG if the 3.3 V plane extends near
the DRCG. However, if a 3.3 V trace must be used, it should originate at the clock synthesizer and
be routed as shown in Figure 18. The maximum routing length for the 3VMRef and 3VMRef#
signals is 8 inches.
Note: The following recommendations assume routing of the reference clocks as microstrip traces.

Figure 18. VddIR and 3VMRef Routing

6 m ils
Ground
NOTE: 3VMRef# should be routed in a similar manner as 3VMRef.
48
6 m ils
VddiR
6 m ils 6 m ils
4.5 m ils
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Intel Pentium 4 Processor / Intel
6 m ils
Ground
6 m ils
Ground/Power Plane
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850 Chipset Family Platform Design Guide
6 m ils 6 m ils
3VMRef Ground
6 m ils
VddIR_3VMRef_route
R