Intel Pentium 4 Design Manual page 14

Introduction
Tables
Table 1. Platform Conventions and Terminology .............................................................. 19
Table 2. Intel
Table 3. Placement Assumptions for the Desktop Configuration (6-Layer Motherboard). 31
Table 4. Placement Assumptions for the Desktop Configuration (4-Layer Motherboard). 32
Table 5. BCLK [1:0] Routing Guidelines............................................................................ 43
Table 6. Rambus RDRAM* Device Clock Routing Guidelines.......................................... 50
Table 7. Rambus DRCG* Impedance Matching Network Values ..................................... 54
Table 8. 66 MHz Clock Routing Length Guidelines........................................................... 57
Table 9. 33 MHz Clock Routing Guidelines....................................................................... 58
Table 10. System Bus Routing Summary for the Processor............................................. 61
Table 11. Source Synchronous Signal Groups and the Associated Strobes .................... 64
Table 12. Processor Package Lengths ............................................................................. 66
Table 13. Miscellaneous Signals (Signals That Are Not Data, Address, or Strobe)
Table 14. Layout Recommendations for FERR# Signals (Topology 1a) .......................... 72
Table 15. Layout Recommendations for PROCHOT# and THERMTRIP# Signals
(Topology 1b) ............................................................................................................. 73
Table 16. Layout Recommendations for Miscellaneous Signals (Topology 2) ................. 73
Table 17. Layout Recommendations for INIT# (Topology 2A).......................................... 74
Table 18. Layout Recommendations for Miscellaneous Signals (Topology 2B) ............... 75
Table 19: BR0# and RESET# Lengths.............................................................................. 76
Table 20. Reference Voltage Network Values .................................................................. 83
Table 21. Direct Rambus Channel Signal Groups ............................................................ 91
Table 22. Direct Rambus RSL Signal Lengths for Rambus RIMM* Connectors on
Motherboard............................................................................................................... 92
Table 23. RSL and Clocking Signal Rambus RIMM* Connector Capacitance
Requirement .............................................................................................................. 99
Table 24. Copper Tab Area Calculation .......................................................................... 100
Table 25. AGP 2.0 Signal Groups ................................................................................... 113
Table 26. AGP 2.0 Routing Summary............................................................................. 116
Table 27. AGP Pull-up/Pull-down Resistors.................................................................... 120
Table 28. 3.3 V and 5 V Tolerant Signals during 1.5 V Operation .................................. 121
Table 29 List of Vendors for Retention Mechanism ........................................................ 123
Table 30. 8-Bit Hub Interface Buffer Configuration Setting ............................................. 128
Table 31. 8-Bit Hub Interface HUBREF Generation Circuit Specifications ..................... 128
Table 32. 8-Bit Hub Interface RCOMP Resistor Values.................................................. 130
Table 33. Intel
Table 34. Signal Descriptions.......................................................................................... 147
Table 35. Codec Configurations...................................................................................... 148
Table 36. Integrated LAN Options................................................................................... 162
Table 37. LAN Design Guide Section Reference............................................................ 163
Table 38. Length Requirements for Single Solution Interconnect................................... 165
Table 39. Length Requirements for LOM/CNR Interconnect .......................................... 165
Table 40. Critical Dimension Values ............................................................................... 174
Table 41. Critical Dimension Values ............................................................................... 177
Table 42. Decoupling Capacitor Recommendation......................................................... 186
Table 43. IOAPIC Interrupt Inputs 16 Through 23 Usage ............................................... 189
Table 44. Reference Solution Fan Power Header Pinout ............................................... 195
Table 45. Boxed Processor Fan Power Header Pinout .................................................. 195
Table 46. Decoupling Requirements ............................................................................... 200
Table 47. Decoupling Locations ...................................................................................... 200
Table 48. Four-Phase Decoupling Requirements ........................................................... 202
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ICH2 Codec Options.................................................................................. 25
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AC'97 SDIN Pull-down Resistors........................................................... 144
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Intel Pentium 4 Processor / Intel
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850 Chipset Family Platform Design Guide
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1,3
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