Rtc; Lan* Connect Interface - Intel Pentium 4 Design Manual

Layout Review Checklist
16.11

RTC

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16.12

LAN* Connect Interface

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288
Recommendations
• RTC LEAD length ≤ 0.25 inches Max
• Minimize capacitance between Xin and Xout
• Put GND plane underneath crystal
components
• Do not route switching signals under the
external components (unless on other side
of board)
Recommendations
• Stack-up: 5 mils wide, 10 mil spacing
• Z = 60 Ω +15%
O
• LAN Max Trace Length ICH2 to CNR:
L = 3 inches to 9 inches (0.5 inches to
3 inches on card)
• Stubs due to R-pak CNR/LOM stuffing
option should not be present.
• Maximum Trace Lengths: ICH2 to
82562EH/ET/EM : L = 4.5 inches to
8.5 inches
• Max mismatch between the length of a
clock trace and the length of any data trace
is 0.5 inches
• Maintain constant symmetry and spacing
between the traces within a differential pair.
• Keep the total length of each differential pair
under 4 inches.
• Do not route the transmit differential traces
closer than 70 mils to the receive
differential traces.
• Distance between differential traces and
any other signal line is 70 mils.
• Keep Max separation between differential
pairs to 7 mils.
• Differential trace impedance should be
controlled to be ~100 ohms.
• For high-speed signals, the number of
corners and vias should be kept to a
minimum. If a 90 degree bend is required, it
is recommended to use two 45 degree
bends.
® ®
Intel Pentium 4 Processor / Intel
Reason/Impact
• Refer to Section 9.8.3.
• Refer to Section 9.8.3.
• Refer to Section 9.8.3.
• Refer to Section 9.8.3.
Reason/Impact
• Signal integrity requirement.
• To meet timing requirements.
• To minimize inductance.
• To meet timing requirements.
• To meet timing and signal quality
requirements.
• To meet timing and signal quality
requirements.
• Issues found with traces longer than 4
inches : IEEE phy conformance failures,
excessive EMI and or degraded receive
BER.
• To minimize cross-talk.
• To minimize cross-talk.
• To meet timing and signal quality
requirements.
• To meet timing and signal quality
requirements.
• To meet timing and signal quality
requirements.
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850 Chipset Family Platform Design Guide
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