Routing Guidelines For System Bus Clocks; Figure 12. Processor Bclk Topology - Intel Pentium 4 Design Manual

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Routing Guidelines for System Bus Clocks

The CK00 clock synthesizer provides four sets of 100 MHz differential clock outputs. The
100 MHz differential clocks are driven to the processor and MCH as shown in Figure 12.

Figure 12. Processor BCLK Topology

NOTE: Connect the CK00 component's HOST pin to the BCLK0 pins on the processor and MCH. Additionally,
connect the CK00 HOST_BAR pin to the BCLK1 pins.
The CK00 clock driver differential bus output structure is a "Current Mode Current Steering"
output that develops a clock signal by alternately steering a programmable constant current to the
external termination resistors Rt. The resulting amplitude is determined by multiplying I
value of Rt. The current I
the amplitude of the clock signal can be adjusted for different values of Rt to match impedances or
to accommodate future load requirements.
The recommended termination for the CK00 differential bus clock is a "Shunt Source
termination." Refer to Figure 13 for an illustration of this terminology scheme. Parallel Rt resistors
perform a dual function, converting the current output of the CK00 to a voltage and matching the
driver output impedance to the transmission line. The series resistors Rs provide isolation from the
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Intel Pentium 4 Processor / Intel
Clock Driver
CK00
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is programmable by a resistor and an internal multiplication factor so
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850 Chipset Family Platform Design Guide
Platform Clock Routing Guidelines
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