Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet
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Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet

Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet

Pentium 4 processor 6x1 sequence, on 65 nm process in the 775-land lga package supporting hyper-threading technology and 64 arhitecture
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®
®
Intel
Pentium
4 Processor
∆
6x1
Sequence
Datasheet
– On 65 nm Process in the 775-land LGA Package supporting
®
Hyper-Threading Technology and Intel
64 architecture
January 2007
Document Number: 310308-002

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Summary of Contents for Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor

  • Page 1 ® ® Intel Pentium 4 Processor ∆ Sequence Datasheet – On 65 nm Process in the 775-land LGA Package supporting ® Hyper-Threading Technology and Intel 64 architecture January 2007 Document Number: 310308-002...
  • Page 2 Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information. Intel, Pentium, Intel NetBurst Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

  • Page 3: Table Of Contents

    Contents Introduction .......................9 Terminology ..................... 10 1.1.1 Processor Packaging Terminology ............. 10 References ....................... 11 Electrical Specifications ................13 Power and Ground Lands..................13 Decoupling Guidelines ..................13 2.2.1 Decoupling ..................13 2.2.2 Decoupling ..................13 2.2.3 FSB Decoupling..................14 Voltage Identification ..................
  • Page 4 5.2.5 THERMTRIP# Signal ................82 5.2.6 and Fan Speed Reduction ............82 CONTROL 5.2.7 Thermal Diode..................82 Features ......................85 Power-On Configuration Options ................85 Clock Control and Low Power States ..............85 6.2.1 Normal State ..................86 6.2.2 HALT and Enhanced HALT Powerdown States..........86 6.2.2.1 HALT Powerdown State ..............86 6.2.2.2 Enhanced HALT Powerdown State..........87 6.2.3...
  • Page 5 Figures Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors..............21 Overshoot Example Waveform ................22 Phase Lock Loop (PLL) Filter Requirements ..............31 Processor Package Assembly Sketch ................33 Processor Package Drawing Sheet 1 of 3 ..............34 Processor Package Drawing Sheet 2 of 3 ..............
  • Page 6 Tables References ......................11 Voltage Identification Definition ..................15 Absolute Maximum and Minimum Ratings ..............17 Voltage and Current Specification ................18 Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors ..............20 Overshoot Specifications..................21 FSB Signal Groups ....................23 Signal Characteristics....................24 Signal Reference Voltages ..................24 GTL+ Signal Group DC Specifications ................25 GTL+ Asynchronous Signal Group DC Specifications ............25 PWRGOOD and TAP Signal Group DC Specifications............26...

  • Page 7: Revision History

    Revision History Revision No. Description Date of Release -001 • Initial release January 2006 -002 • Added Intel Pentium 4 processor 651, 641, and 631 at 65 W. January 2007 § Datasheet...
  • Page 8 Pentium 4 processor family supporting Hyper-Threading Technology (HT Technology) delivers Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel ® NetBurst microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance.

  • Page 9: Introduction

    Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s. Intel will enable support components for the Pentium 4 processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.

  • Page 10: Terminology

    FSB is not in use. This feature is always enabled on the processor. ® ® Enhanced Intel SpeedStep technology allows trade-offs to be made between performance and power consumptions. This may lower average power consumption (in conjunction with OS support).

  • Page 11: References

    ® ® ® Intel Pentium D Processor, Intel Pentium Processor ® ® Extreme Edition, and Intel Pentium 4 Processor Thermal http://www.intel.com/design/ and Mechanical Design Guidelines pentiumXE/designex/ 306830.htm NOTE: Refer to this document for 86 W processors. ® Intel Core™2 Duo Desktop Processor E6000 Sequence and ®...
  • Page 12 Introduction Datasheet...

  • Page 13: Electrical Specifications

    Electrical Specifications Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. Power and Ground Lands The Pentium 4 processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs for on-chip power distribution.

  • Page 14: Fsb Decoupling

    Processor Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced HALT State).

  • Page 15: Voltage Identification Definition

    Electrical Specifications Table 2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID5 VID4 VID3 VID2 VID1 VID0 0.8375 1.2125 0.8500 1.2250 0.8625 1.2375 0.8750 1.2500 0.8875 1.2625 0.9000 1.2750 0.9125 1.2875 0.9250 1.3000 0.9375 1.3125 0.9500 1.3250 0.9625 1.3375 0.9750 1.3500...

  • Page 16: Reserved, Unused, And Testhi Signals

    Electrical Specifications Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to V , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

  • Page 17: Voltage And Current Specification

    Electrical Specifications Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.

  • Page 18: Dc Voltage And Current Specification

    Electrical Specifications 2.5.2 DC Voltage and Current Specification Table 4. Voltage and Current Specification 1, 2 Symbol Parameter Unit Notes VID Range 1.200 — 1.3375 Processor for 775_VR_CONFIG_05A number Refer to Table 5 4, 5, 6 3.6 GHz Figure 1 3.4 GHz 3.2 GHz 3 GHz...
  • Page 19 VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced HALT State). These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required.

  • Page 20: And For 775_Vr_Config_06 Processors

    Electrical Specifications Table 5. Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors 1,2,3,4 Voltage Deviation from VID Setting (V) Maximum Voltage Typical Voltage Minimum Voltage 1.7 mΩ 1.75 mΩ 1.8 mΩ 0.000 -0.019 -0.038 -0.009 -0.028 -0.047 -0.017 -0.037 -0.056...

  • Page 21: Vcc Overshoot

    Electrical Specifications Figure 1. Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and for 775_VR_CONFIG_06 Processors Icc [A] VID - 0.000 VID - 0.019 VID - 0.038 Vcc Maximum VID - 0.057 VID - 0.076 VID - 0.095 VID - 0.114 Vcc Typical VID - 0.133 VID - 0.152...

  • Page 22: Die Voltage Validation

    GTLREF specifications). Termination resistors (R ) for GTL+ signals are provided on the processor silicon and are terminated to V . Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

  • Page 23: Fsb Signal Groups

    Electrical Specifications 2.6.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving.

  • Page 24: Signal Characteristics

    Electrical Specifications Table 7. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals Synchronous to TAP Output FSB Clock Clock BCLK[1:0], ITP_CLK[1:0] VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[1:0], COMP[5:4,1:0], RESERVED, TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, Power/Other VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR# VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT,...

  • Page 25: Gtl+ Asynchronous Signals

    Electrical Specifications 2.6.2 GTL+ Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0-to-1 transition) by the processor.

  • Page 26: Pwrgood And Tap Signal Group Dc Specifications

    Electrical Specifications Table 11. GTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Unit Notes Input Leakage ± 200 µA Current Output Leakage ± 200 µA Current Buffer On Resistance NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.

  • Page 27: Vttpwrgd Dc Specifications

    Electrical Specifications Table 13. VTTPWRGD DC Specifications Symbol Parameter Unit Input Low Voltage — — Input High Voltage — — Table 14. BSEL[2:0] and VID[5:0] DC Specifications 1, 2 Symbol Parameter Unit Notes (BSEL) Buffer On Resistance Ω (VID) Buffer On Resistance Ω...

  • Page 28: Gtl+ Front Side Bus Specifications

    Electrical Specifications 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF.

  • Page 29: Clock Specifications

    Refer to Table 17 for the processor supported ratios. The processor uses a differential clocking implementation. For more information on processor clocking, contact your Intel representative. Table 17. Core Frequency to FSB Multiplier Configuration Core Frequency Multiplication of System Core...

  • Page 30: Fsb Frequency Select Signals (Bsel[2:0])

    Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer.

  • Page 31: Phase Lock Loop (Pll) Filter Requirements

    Electrical Specifications Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB 1 Hz fpeak 1 MHz 66 MHz fcore Passband High Frequency Band Filter_Spec NOTES: Diagram not to scale. No specification for frequencies beyond fcore (core frequency).

  • Page 32: Bclk[1:0] Specifications

    Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 19. Front Side Bus Differential BCLK Specifications Symbol Parameter Unit Notes Input Low Voltage -0.150 0.000 Input High Voltage 0.660 0.700 0.850 2, 3 Absolute Crossing Point 0.250 0.550 CROSS(abs) 0.250 + 0.550 + 3, 4, 5 Relative Crossing Point CROSS(rel)

  • Page 33: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications The Pentium 4 processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.

  • Page 34: Processor Package Drawing Sheet 1 Of 3

    Package Mechanical Specifications Figure 5. Processor Package Drawing Sheet 1 of 3 Datasheet...

  • Page 35: Processor Package Drawing Sheet 2 Of 3

    Package Mechanical Specifications Figure 6. Processor Package Drawing Sheet 2 of 3 Datasheet...

  • Page 36: Processor Package Drawing Sheet 3 Of 3

    Package Mechanical Specifications Figure 7. Processor Package Drawing Sheet 3 of 3 Datasheet...

  • Page 37: Processor Component Keep-Out Zones

    Package Mechanical Specifications Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate.

  • Page 38: Package Insertion Specifications

    This diagram is to aid in the identification of the Pentium 4 processor. Figure 8. Processor Top-Side Markings Example Brand Processor Number/ S-Spec/ Country of Assy INTEL © ‘05 XXXXXXXX Frequency/L2 Cache/Bus/ 641 SLxxx [COO] 775_VR_CONFIG_05x 3.20GHZ/2M/800/05A...

  • Page 39: Processor Land Coordinates

    Package Mechanical Specifications Processor Land Coordinates Figure 9 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 9. Processor Land Coordinates and Quadrants (Top View) VCC / VSS Socket 775 Quadrants Address/ Top View...
  • Page 40 Package Mechanical Specifications Datasheet...

  • Page 41: Land Listing And Signal Descriptions

    Land Listing and Signal Descriptions Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown Figure 10 Figure 11.

  • Page 42: Land-Out Diagram (Top View - Left Side)

    Land Listing and Signal Descriptions Figure 10.land-out Diagram (Top View – Left Side) DP3# DP0# BSEL1 FC15 DP2# DP1# BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD D43# D41#...

  • Page 43: Land-Out Diagram (Top View - Right Side)

    Land Listing and Signal Descriptions Figure 11.land-out Diagram (Top View – Right Side) VSS_MB_ VCC_MB_ VSS_ VCC_ FC16 REGULATION REGULATION SENSE SENSE FC12 VTTPWRGD FC11 VID2 VID0 VID3 VID1 VID5 PROCHOT# THERMDA VID4 ITP_CLK0 THERMDC A35# A34# ITP_CLK1 BPM0# BPM1# A33# A32# RSVD...

  • Page 44: Alphabetical Land Assignments

    Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type A10# Source Synch Input/Output BCLK0 Clock Input A11# Source Synch Input/Output BCLK1 Clock Input A12# Source Synch Input/Output...
  • Page 45 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D26# Source Synch Input/Output D61# Source Synch Input/Output D27# Source Synch Input/Output D62# Source Synch Input/Output D28# Source Synch Input/Output...
  • Page 46 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type FC18 Power/Other Output RESERVED FC20 Power/Other Output RESERVED Power/Other Output RESERVED FERR#/PBE# Asynch GTL+ Output RESERVED GTLREF0...
  • Page 47 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type TRST# Input Power/Other Power/Other Power/Other Power/Other AG11 Power/Other AC23 Power/Other AG12 Power/Other AC24 Power/Other AG14 Power/Other...
  • Page 48 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AJ19 Power/Other AM21 Power/Other AJ21 Power/Other AM22 Power/Other AJ22 Power/Other AM25 Power/Other AJ25 Power/Other AM26 Power/Other...
  • Page 49 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 50 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type VID3 Power/Other Output Power/Other VID4 Power/Other Output Power/Other VID5 Power/Other Output Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 51 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AG16 Power/Other AK28 Power/Other AG17 Power/Other AK29 Power/Other AG20 Power/Other AK30 Power/Other AG23 Power/Other Power/Other AG24...
  • Page 52 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 53 Land Listing and Signal Descriptions Table 23.Alphabetical Land Table 23.Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS_MB_ Power/Other Output REGULATION Power/Other VSS_SENSE Power/Other Output Power/Other...

  • Page 54: Numerical Land Assignment

    Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D08# Source Synch Input/Output A21# Source Synch Input/Output D09# Source Synch Input/Output A23# Source Synch Input/Output Power/Other Power/Other...
  • Page 55 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AD24 Power/Other Power/Other AD25 Power/Other SKTOCC# Power/Other Output AD26 Power/Other Power/Other AD27 Power/Other Output AD28 Power/Other...
  • Page 56 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AG16 Power/Other AH25 Power/Other AG17 Power/Other AH26 Power/Other AG18 Power/Other AH27 Power/Other AG19 Power/Other AH28 Power/Other...
  • Page 57 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other AL16 Power/Other Power/Other AL17 Power/Other Power/Other AL18 Power/Other THERMDC Power/Other AL19 Power/Other AK10 Power/Other PROCHOT#...
  • Page 58 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AM25 Power/Other VSS_MB_ Power/Other Output REGULATION AM26 Power/Other FC16 Power/Other Output AM27 Power/Other Power/Other AM28 Power/Other...
  • Page 59 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D51# Source Synch Input/Output Power/Other Power/Other Power/Other DSTBP3# Source Synch Input/Output Power/Other D54# Source Synch Input/Output Power/Other Power/Other...
  • Page 60 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other DSTBP2# Source Synch Input/Output D19# Source Synch Input/Output Power/Other Input Power/Other DSTBN2# Source Synch Input/Output D23# Source Synch Input/Output...
  • Page 61 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other LINT0 Asynch GTL+ Input FC15 Power/Other Output Power/Other Power/Other Power/Other BSEL1 Power/Other Output Power/Other RSP#...
  • Page 62 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Input STPCLK# Asynch GTL+ Input Power/Other Power/Other Power/Other A07# Source Synch Input/Output Power/Other A05# Source Synch Input/Output...
  • Page 63 Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Table 24.Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other A18# Source Synch Input/Output AP1# Common Clock Input/Output Power/Other Power/Other Power/Other A13# Source Synch Input/Output BOOTSELECT Power/Other...

  • Page 64: Alphabetical Signals Reference

    Land Listing and Signal Descriptions Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information.
  • Page 65 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. BCLK[1:0] Input All external timing parameters are specified with respect to the...
  • Page 66 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this Input/ signal is sampled to determine the agent ID = 0. BR0# Output This signal does not have on-die termination and must be...
  • Page 67 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.
  • Page 68 When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an...
  • Page 69 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating- point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error.
  • Page 70 • Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the ® Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3: System Programming Guide. MSID[1:0] (input) MSID0 is used to indicate to the processor whether the platform supports 775_VR_CONFIG_05B processors.
  • Page 71 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after V and BCLK have reached their proper specifications.

  • Page 72: Vcc

    Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal TESTHI[13:0] Input description) through a resistor for proper processor operation. See Section 2.4 for more details.
  • Page 73 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description VID[5:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (V ). Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more information.
  • Page 74 Land Listing and Signal Descriptions Datasheet...

  • Page 75: Thermal Specifications And Design Considerations

    5.1.1 Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T...

  • Page 76: Processor Thermal Specifications For 775_Vr_Config_05A Processors

    The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption.

  • Page 77: Thermal Profile For 775_Vr_Config_05A Processors

    Thermal Specifications and Design Considerations Table 28. Thermal Profile for 775_VR_CONFIG_05A Processors Power Maximum Power Maximum Power Maximum (°C) (°C) (°C) 44.3 53.0 61.7 44.9 53.6 62.3 45.5 54.2 62.9 46.0 54.7 63.4 46.6 55.3 64.0 47.2 55.9 64.6 47.8 56.5 65.2 48.4...

  • Page 78: Thermal Profile For 775_Vr_Config_06 Processors

    Thermal Specifications and Design Considerations Table 29. Thermal Profile for 775_VR_CONFIG_06 Processors Maximum Maximum Power (W) Power (W) Tc (°C) Tc (°C) 43.6 54.5 44.2 55.1 44.9 55.8 45.5 56.4 46.2 57.0 46.8 57.7 47.4 58.3 48.1 59.0 48.7 59.6 49.4 60.2 50.0...

  • Page 79: Thermal Metrology

    26. This temperature specification is meant to help ensure proper operation of the processor. Figure 14 illustrates where Intel recommends T thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).

  • Page 80: Thermal Monitor 2

    Thermal Specifications and Design Considerations With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable.

  • Page 81: On-Demand Mode

    Thermal Specifications and Design Considerations Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. Note that the Thermal Monitor 2 TCC cannot be activated via the on demand mode.

  • Page 82: Prochot# Signal

    CONTROL thermal diode. The purpose of this feature is to support acoustic optimization through fan speed control. Contact your Intel representative for further details and documentation. 5.2.7 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal "diode", with its collector shorted to Ground.

  • Page 83: Thermal "Diode" Parameters Using Diode Model

    6.24 Ω NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized across a temperature range of 50 – 80 °C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:...

  • Page 84: Thermal "Diode" N

    Thermal Specifications and Design Considerations accomplished using the equations listed under Table 30. In most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode the ideality value (also called n ) will be 1.000.

  • Page 85: Features

    Features Features Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.

  • Page 86: Normal State

    Features Figure 16. Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Enhanced HALT or HALT State Normal State INIT#, BINIT#, INTR, NMI, SMI#, BCLK running Normal execution RESET#, FSB interrupts Snoops and interrupts allowed Snoop Snoop Event...

  • Page 87: Enhanced Halt Powerdown State

    Features The return from a System Management Interrupt (SMI) handler can be to either ® Normal Mode or the HALT Power Down state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume III: System Programmer's Guide for more information.

  • Page 88: Enhanced Halt Snoop Or Halt Snoop State, Stop Grant Snoop State

    Features While in Stop-Grant state, the processor will process a FSB snoop. 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State.

  • Page 89: Boxed Processor Specifications

    Boxed Processor Specifications Boxed Processor Specifications The Intel Pentium 4 processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium 4 processor will be supplied with a cooling solution.

  • Page 90: Space Requirements For The Boxed Processor (Side View; Applies To All Four Side Views)

    Boxed Processor Specifications Figure 18. Space Requirements for the Boxed Processor (Side View; applies to all four side views) 95.0 [3.74] 81.3 [3.2] 10.0 25.0 [0.39] [0.98] Sid Vi Figure 19. Space Requirements for the Boxed Processor (Top View) 95.0 [3.74] 95.0 [3.74]...

  • Page 91: Boxed Processor Fan Heatsink Weight

    Boxed Processor Specifications Figure 20. Space Requirements for the Boxed Processor (Overall View) 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements.

  • Page 92: Boxed Processor Fan Heatsink Power Cable Connector Description

    Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 22 shows the location of the fan power connector relative to the processor socket.

  • Page 93: Thermal Specifications

    Boxed Processor Specifications Figure 22. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.

  • Page 94: Boxed Processor Fan Heatsink Airspace Keep-Out Requirements

    Boxed Processor Specifications Figure 23. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View) Figure 24. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 2 View) § § Datasheet...

  • Page 95: Balanced Technology Extended (Btx) Boxed Processor Specifications

    (BTX) Boxed Processor Specifications The Intel Pentium 4 processors will be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from largely standard components. The boxed Intel Pentium 4 processor will be supplied with a cooling solution known as the Thermal Module Assembly (TMA).

  • Page 96: Mechanical Specifications

    Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Intel Pentium 4 processor TMA. The boxed processor will be shipped with an unattached TMA. Figure 27 shows a mechanical representation of the boxed Pentium 4 processor in the 775-land package for Type I TMA.

  • Page 97: Requirements For The Balanced Technology Extended (Btx) Type I Keep-Out Volumes

    Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 27. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Datasheet...

  • Page 98: Boxed Processor Thermal Module Assembly Weight

    Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 28. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. 8.1.2 Boxed Processor Thermal Module Assembly Weight The boxed processor thermal module assembly for Type I BTX will not weigh more than...

  • Page 99: Electrical Requirements

    Balanced Technology Extended (BTX) Boxed Processor Specifications Document, Balanced Technology Extended (BTX) System Design Guide, and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for more detailed information regarding the support and retention module and chassis interface and keepout zones. Figure 29 illustrates the assembly stack including the SRM.

  • Page 100: Boxed Processor Tma Power Cable Connector Description

    Balanced Technology Extended (BTX) Boxed Processor Specifications Note: The boxed processor’s TMA requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the TMA power cable to reach it.

  • Page 101: Thermal Specifications

    Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 31. Balanced Technology Extended (BTX) Mainboard Power Header Placement (Hatched Area) Thermal Specifications This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor. 8.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a TMA.

  • Page 102: Variable Speed Fan

    Balanced Technology Extended (BTX) Boxed Processor Specifications In addition, Type I TMA must be used with Type I chassis only and Type II TMA with Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height difference.

  • Page 103: Tma Set Points For 3-Wire Operation Of Btx Type I And Type Ii Boxed Processors

    As processor power has increased, the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.
  • Page 104 Balanced Technology Extended (BTX) Boxed Processor Specifications Datasheet...

  • Page 105: Debug Tools Specifications

    Debug Tools Specifications Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature.
  • Page 106 Debug Tools Specifications Datasheet...

This manual is also suitable for:

Pentium 4 631Pentium 4 641Pentium 4 651Pentium 4 661

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