Via Compensation - Intel Pentium 4 Design Manual

R
Listed below are a few definitions.
• Package Dimension (∆ ∆ ∆ ∆ L
• Board Trace Length (L
• Nominal Length: the length to which all signals are matched.
As Figure 59 shows, L1 plus L3 must be length matched to L2 plus L4 within ±10 mils.
Equation 2. Compensated Trace Length Calculation
∆ L = ( ∆ L
PCB
The PCB trace length for each signal is a calculated value, and may vary with designs. The
nominal MCH package trace velocity is 167.64 ps/in. The PCB
dependent. PCB
route the RSL channel. Below is the PCB
the Intel 850 chipset customer reference board (CRB).
• Stripline velocity typically equals 172 ps/in
• Microstrip velocity typically equals 154 ps/in
The MCH package trace length information is contained in the Intel
Controller Hub (MCH) Datasheet. The package trace length information presented in this
document is normalized to the longest package trace length. The RSL and clocking signal lengths
(∆L ) can be renormalized to any signal using Equation 3.
PKG
Equation 3. Normalized Trace Length Calculation
New ∆ L
It is not necessary to account for CMOS signals package compensation. For PCB routing, the
mismatch between the CMOS signals (CMD, SCK) and the RSL signals should be kept as
minimum as possible.
6.1.2.2

Via Compensation

All RSL and clocking signals must have the same number of vias. As a result, each trace will have
at least one via because some of the RSL signals must be routed on other layers of the
motherboard. The via should be placed as close as possible to the MCH package ball. For the
channel routed on outer layers (microstrip), it will be necessary to place "dummy" via on all
signals routed on the top layer. The electrical characteristics between "dummy" and "real" vias are
not exact, so additional compensation is needed on each signal that has "dummy" vias.
"Dummy" vias are not required on the channel routed on the inner layers (stripline) because all
signals will require a "real" via.
Each signal with a dummy via must have 25 mils of additional trace length . The additional 25 mils
trace length must be added to the signal routed on the top layer, after length matching.
"Real" via = "Dummy" via + 25 mils of trace length
® ®
Intel Pentium 4 Processor / Intel
): a representation of the length from the pad to the ball.
PKG
): the trace length on the board.
MB
* Package
PKG TRACE VELOCITY
can change depending on which layer the board designer plans to
TRACE VELOCITY
= ∆ L - ∆ L
PKG PKG NORMALIZED RSL
®
850 Chipset Family Platform Design Guide
) / PCB
TRACE VELOCITY
TRACE VELOCITY
for stripline and microstrip routing used on
TRACE VELOCITY
Memory Interface Routing
is board and layer
®
850 Chipset: 82850 Memory
95