GE MiCOM P40 Technical Manual page 25

Table of Figures
Figure 1: P40L family - version evolution
Figure 2: Key to logic diagrams
Figure 3: Functional Overview
Figure 4: Hardware architecture
Figure 5: Exploded view of IED
Figure 6: Front panel (40TE)
Figure 7: Rear view of populated case
Figure 8: Rear connection to terminal block
Figure 9: Main processor board
Figure 10: Power supply board
Figure 11: Power supply assembly
Figure 12: Power supply terminals
Figure 13: Watchdog contact terminals
Figure 14: Rear serial port terminals
Figure 15: IEC 61850-9-2LE board
Figure 16: Standard output relay board - 8 contacts
Figure 17: IRIG-B board
Figure 18: Fibre optic board
Figure 19: Rear communication board
Figure 20: Ethernet board
Figure 21: Redundant Ethernet board
Figure 22: Fully populated Coprocessor board
Figure 23: High Break relay output board
Figure 24: High Break contact operation
Figure 25: Software Architecture
Figure 26: Frequency response of FIR filters
Figure 27: Frequency Response (indicative only)
Figure 28: Navigating the HMI
Figure 29: Default display navigation
Figure 30: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
Figure 31: Comparison of Conventional IED and Sampled Values IED
Figure 32: Data sampling using an IEC 61850-9-2LE interface
Figure 33: System Impedance Ratio
Figure 34: Directional mho element construction
Figure 35: Offset Mho characteristic
Figure 36: Directional Mho element construction - impedance domain
Figure 37: Offset Mho characteristics - impedance domain
Figure 38: Offset mho characteristics - voltage domain
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