Page 1 GE Energy Connections Grid Solutions MiCOM P40 Agile P543i/P545i Technical Manual Single Breaker Current Differential (with Distance) Hardware Version: M Software Version: 85 Publication Reference: P54x1i-TM-EN-1...
Page 3: Table Of Contents
Contents Chapter 1 Introduction Chapter Overview Foreword Target Audience Typographical Conventions Nomenclature Compliance Product Scope Product Versions 3.1.1 Ordering Options Features and Functions Current Differential Protection Functions Distance Protection Functions Protection Functions Control Functions Measurement Functions Communication Functions Logic Diagrams Functional Overview Chapter 2 Safety Information...
Page 4 Contents P543i/P545i 4.1.1 Front Panel Compartments 4.1.2 Keypad 4.1.3 Front Serial Port (SK1) 4.1.4 Front Parallel Port (SK2) 4.1.5 Fixed Function LEDs 4.1.6 Function Keys 4.1.7 Programable LEDs Rear Panel Boards and Modules PCBs Subassemblies Main Processor Board Power Supply Board 6.4.1 Watchdog 6.4.2...
Page 5 P543i/P545i Contents 5.11 Function Key Interface Chapter 5 Configuration Chapter Overview Settings Application Software Using the HMI Panel Navigating the HMI Panel Getting Started Default Display Default Display Navigation Password Entry Processing Alarms and Records Menu Structure Changing the Settings Direct Access (The Hotkey menu) 3.9.1 Setting Group Selection Using Hotkeys...
Page 6 Contents P543i/P545i 10.4.1 Fifth Harmonic Blocking 10.5 Logic for Feeders with In-Zone Transformers 10.6 Second Harmonic Blocking Logic 10.7 Fifth Harmonic Blocking Logic Current Differential Intertripping Stub Bus Differential Protection Application Notes 13.1 Setting Up the Phase Differential Characteristic 13.2 Sensitivity Under Heavy Loads 13.3 Permissive Intertripping...
Page 7 P543i/P545i Contents Cross Country Fault Protection Delta Directional Element Delta Directional Principle and Setup Delta Directional Decision Distance Isolated and Compensated Systems Peterson Coil Earthed Systems Earth Fault Distance Protection for Isolated and Compensated Systems 6.2.1 Single-phase to Earth Faults on Isolated or Compensated Systems 6.2.2 Cross-Country Faults on Isolated or Compensated Systems Implementation of Distance Protection for Isolated and Compensated Networks...
Page 8 Contents P543i/P545i Current Reversal Guard Logic Aided Distance Blocking Schemes Aided Distance Unblocking Schemes Aided Distance Logic Diagrams 4.7.1 Aided Distance Send Logic 4.7.2 Carrier Aided Schemes Receive Logic 4.7.3 Aided Distance Tripping Logic 4.7.4 PUR Aided Tripping logic 4.7.5 POR Aided Tripping logic 4.7.6 Aided Scheme Blocking 1 Tripping logic...
Page 9 P543i/P545i Contents Trip On Close Schemes Switch On To Fault (SOTF) 4.1.1 Switch Onto Fault Mode 4.1.2 SOTF Tripping 4.1.3 SOTF Tripping with CNV Trip On Reclose (TOR) 4.2.1 Trip On Reclose Mode 4.2.2 TOR Tripping Logic for Appropriate Zones 4.2.3 TOR Tripping Logic with CNV Polarisation during Circuit Engergisation...
Page 10 Contents P543i/P545i Autoreclose System Map Diagrams Autoreclose Internal Signals Autoreclose DDB Signals Logic Modules Circuit Breaker Status Monitor 5.1.1 CB State Monitor Logic diagram Circuit Breaker Open Logic 5.2.1 Circuit Breaker Open Logic Diagram Circuit Breaker in Service Logic 5.3.1 Circuit Breaker in Service Logic Diagram 5.3.2 Autoreclose OK Logic Diagram...
Page 11 P543i/P545i Contents 5.22 Monitor Checks for CB Closure 5.22.1 Check Synchronisation Monitor for CB Closure 5.22.2 Voltage Monitor for CB Closure 5.23 Synchronisation Checks for CB Closure 5.23.1 Three-phase Autoreclose System Check Logic Diagram 5.23.2 CB Manual Close System Check Logic Diagram Setting Guidelines De-ionising Time Guidance Dead Timer Setting Guidelines...
Page 12 Contents P543i/P545i Sensitive Earth Fault Protection Logic Application Notes 5.4.1 Insulated Systems 5.4.2 Setting Guidelines (Insulated Systems) High Impedance REF High Impedance REF Principle Thermal Overload Protection Single Time Constant Characteristic Dual Time Constant Characteristic Thermal Overload Protection Implementation Thermal Overload Protection Logic Application Notes 7.5.1 Setting Guidelines for Dual Time Constant Characteristic...
Page 13 P543i/P545i Contents Overfrequency Protection 2.2.1 Overfrequency Protection Implementation 2.2.2 Overfrequency Protection logic 2.2.3 Application Notes Independent R.O.C.O.F Protection Indepenent R.O.C.O.F Protection Implementation Independent R.O.C.O.F Protection Logic Chapter 16 Current Transformer Requirements Chapter Overview Recommended CT Classes Current Differential Requirements Distance Protection Requirements Determining Vk for IEEE C-class CT Worked Examples Calculation of Primary X/R ratio...
Page 14 Contents P543i/P545i Reset Lockout Alarm CB Condition Monitoring Logic Reset Circuit Breaker Lockout 5.7.1 Reset CB Lockout Logic Diagram Application Notes 5.8.1 Setting the Thresholds for the Total Broken Current 5.8.2 Setting the thresholds for the Number of Operations 5.8.3 Setting the thresholds for the Operating Time 5.8.4 Setting the Thresholds for Excesssive Fault Frequency...
Page 15 P543i/P545i Contents Standard CTS Logic CTS Blocking Application Notes 4.6.1 Setting Guidelines 4.6.2 Differential CTS Setting Guidelines Trip Circuit Supervision Trip Circuit Supervision Scheme 1 5.1.1 Resistor Values 5.1.2 PSL for TCS Scheme 1 Trip Circuit Supervision Scheme 2 5.2.1 Resistor Values 5.2.2 PSL for TCS Scheme 2...
Page 16 Contents P543i/P545i Chapter Overview Introduction Teleprotection Scheme Principles Direct Tripping Permissive Tripping Implementation Configuration Connecting to Electrical InterMiCOM Short Distance Long Distance Application Notes Chapter 22 Communications Chapter Overview Communication Interfaces Serial Communication EIA(RS)232 Bus EIA(RS)485 Bus 3.2.1 EIA(RS)485 Biasing Requirements K-Bus Standard Ethernet Communication Hot-Standby Ethernet Failover...
Page 17 P543i/P545i Contents 5.9.9 End of Session 5.10 Switch Manager 5.10.1 Installation 5.10.2 Setup 5.10.3 Network Setup 5.10.4 Bandwidth Used 5.10.5 Reset Counters 5.10.6 Check for Connected Equipment 5.10.7 Mirroring Function 5.10.8 Ports On/Off 5.10.9 VLAN 5.10.10 End of Session Simple Network Management Protocol (SNMP) SNMP Management Information Bases Main Processor MIBS Structure Redundant Ethernet Board MIB Structure...
Page 18 Contents P543i/P545i 7.4.8 Mapping GOOSE Messages to Virtual Inputs 7.4.9 Ethernet Functionality 7.4.10 IEC 61850 Configuration 7.4.11 IEC 61850 Edition 2 Read Only Mode IEC 60870-5-103 Protocol Blocking Courier Protocol Blocking IEC 61850 Protocol Blocking Read-Only Settings Read-Only DDB Signals Time Synchronisation Demodulated IRIG-B 9.1.1...
Page 19 P543i/P545i Contents Unpacking the Goods Storing the Goods Dismantling the Goods Mounting the Device Flush Panel Mounting Rack Mounting Cables and Connectors Terminal Blocks Power Supply Connections Earth Connnection Current Transformers Voltage Transformer Connections Watchdog Connections EIA(RS)485 and K-Bus Connections IRIG-B Connection Opto-input Connections 4.10...
Page 20 Contents P543i/P545i 5.1.4 External Wiring 5.1.5 Watchdog Contacts 5.1.6 Power Supply Product Checks with the IED Energised 5.2.1 Watchdog Contacts 5.2.2 Test LCD 5.2.3 Date and Time 5.2.4 Test LEDs 5.2.5 Test Alarm and Out-of-Service LEDs 5.2.6 Test Trip LED 5.2.7 Test User-programmable LEDs 5.2.8...
Page 21 P543i/P545i Contents 12.2.4 Zone 3 Reach Check 12.2.5 Zone 4 Reach Check 12.2.6 Zone P Reach Check 12.2.7 Zone Q Reach Check 12.2.8 Resistive Reach 12.2.9 Load Blinder 12.3 Operation and Contact Assignment 12.3.1 Phase A 12.3.2 Phase B 12.3.3 Phase C 12.3.4 Time Delay Settings...
Page 22 Contents P543i/P545i 19.1.3 Communications using P59x Interface Units 19.2 Remove Remote Loopbacks 19.3 Verify Communication between IEDs End-to-End Scheme Tests 20.1 Aided Scheme 1 20.1.1 Preparation at Remote End 20.1.2 Performing the Test 20.1.3 Channel Check in the Opposite Direction 20.2 Aided Scheme 2 Onload Checks...
Page 23 P543i/P545i Contents Mal-operation during testing 3.6.1 Failure of Output Contacts 3.6.2 Failure of Opto-inputs 3.6.3 Incorrect Analogue Signals Coprocessor board failures 3.7.1 Signalling failure alarm (on its own) 3.7.2 C diff failure alarm (on its own) 3.7.3 Signalling failure and C diff failure alarms together 3.7.4 Incompatible IED 3.7.5...
Page 24 Contents P543i/P545i Standard Current Transformer Supervision Differential Current Transformer Supervision CB State and Condition Monitoring PSL Timers Measurements and Recording General Disturbance Records Event, Fault and Maintenance Records Fault Locator Ratings AC Measuring Inputs Current Transformer Inputs Voltage Transformer Inputs Auxiliary Supply Voltage Nominal Burden Power Supply Interruption...
Page 25 P543i/P545i Contents 12.3 R&TTE Compliance: 2014/53/EU 12.4 UL/CUL Compliance 12.5 ATEX Compliance: 2014/34/EU Appendix A Ordering Options Appendix B Settings and Signals Appendix C Wiring Diagrams P54x1i-TM-EN-1 xxiii...
Page 26 Contents P543i/P545i xxiv P54x1i-TM-EN-1...
Page 27 Table of Figures Figure 1: P40L version M85 - version evolution Figure 2: Key to logic diagrams Figure 3: Functional Overview Figure 4: Hardware architecture Figure 5: Coprocessor hardware architecture Figure 6: Exploded view of IED Figure 7: Front panel (60TE) Figure 8: Rear view of populated case Figure 9:...
Page 28 Table of Figures P543i/P545i Figure 39: CT Compensation Figure 40: The need for zero-sequence current filtering Figure 41: Magnetising inrush phenomenon Figure 42: Typical overflux current waveform Figure 43: Phase Current Differential Protection logic for feeders with in-zone transformers Figure 44: Second Harmonic Blocking logic Figure 45: Fifth Harmonic Blocking logic...
Page 29 P543i/P545i Table of Figures Figure 78: Biased Neutral Current Detector Characteristic Figure 79: Load Blinder Characteristics Figure 80: Sequence networks connection for an internal A-N fault Figure 81: - DV Forward and Reverse tripping regions Figure 82: Current level (amps) at which transient faults are self-extinguishing Figure 83: Earth fault in Petersen Coil earthed system Figure 84:...
Page 30 Table of Figures P543i/P545i Figure 117: DEF Directional Signals Figure 118: Aided DEF Send logic Figure 119: Carrier Aided Schemes Receive logic Figure 120: Aided DEF Tripping logic Figure 121: POR Aided Tripping logic Figure 122: Aided Scheme Blocking 1 Tripping logic Figure 123: Aided Scheme Blocking 2 Tripping logic Figure 124:...
Page 31 P543i/P545i Table of Figures Figure 157: PSB timer setting guidelines Figure 158: Out of Step detection characteristic Figure 159: Out of Step logic diagram Figure 160: OST setting determination for the positive sequence resistive component OST R5 Figure 161: OST R6max determination Figure 162: Example of timer reset due to MOVs operation Figure 163:...
Page 32 Table of Figures P543i/P545i Figure 197: Autoreclose Shot Counters logic diagram (Module 41) Figure 198: CB Control logic diagram (Module 43) Figure 199: Circuit Breaker Trip Time Monitoring logic diagram (Module 53) Figure 200: AR Lockout Logic Diagram (Module 55) Figure 201: Reset Circuit Breaker Lockout Logic Diagram (Module 57) Figure 202:...
Page 33 P543i/P545i Table of Figures Figure 237: Underfrequency logic (single stage) Figure 238: Overfrequency logic (single stage) Figure 239: Rate of change of frequency logic (single stage) Figure 240: Fault recorder stop conditions Figure 241: Broken Current Accumulator logic diagram Figure 242: CB Trip Counter logic diagram Figure 243: Operating Time Accumulator...
Page 34 Table of Figures P543i/P545i Figure 277: IM64 communications mode and IEEE C37.94 alarm signals Figure 278: IM64 two-terminal scheme extended supervision Figure 279: IM64 three-terminal scheme extended supervision Figure 280: Example assignment of InterMiCOM signals within the PSL Figure 281: Direct connection Figure 282: Indirect connection using modems...
Page 35 P543i/P545i Table of Figures Figure 316: Simulated input behaviour Figure 317: Test example 1 Figure 318: Test example 2 Figure 319: Test example 3 Figure 320: Current Differential Bias Characteristics Figure 321: State impedances Figure 322: Possible terminal block types Figure 323: Front panel assembly P54x1i-TM-EN-1...
Page 36 Table of Figures P543i/P545i xxxiv P54x1i-TM-EN-1...
Page 37: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION...
Page 38 Chapter 1 - Introduction P543i/P545i P54x1i-TM-EN-1...
Page 39: Chapter Overview
P543i/P545i Chapter 1 - Introduction CHAPTER OVERVIEW This chapter provides some general information about the technical manual and an introduction to the device(s) described in this technical manual. This chapter contains the following sections: Chapter Overview Foreword Product Scope Features and Functions Logic Diagrams Functional Overview P54x1i-TM-EN-1...
Page 40: Foreword
Chapter 1 - Introduction P543i/P545i FOREWORD This technical manual provides a functional and technical description of General Electric's P543i/P545i, as well as a comprehensive set of instructions for using the device. The level at which this manual is written assumes that you are already familiar with protection engineering and have experience in this discipline.
Page 41: Nomenclature
P543i/P545i Chapter 1 - Introduction NOMENCLATURE Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout the manual. Some of these terms are well-known industry-specific terms while others may be special product- specific terms used by General Electric. The first instance of any acronym or term used in a particular chapter is explained.
Page 42: Product Scope
Chapter 1 - Introduction P543i/P545i PRODUCT SCOPE The P543 and P545 devices have been designed for current differential protection of overhead line and cable applications. Version M85 of P543 and P545 have been designed for both solidly grounded systems and Petersen Coil grounded systems.
Page 43: Ordering Options
P543i/P545i Chapter 1 - Introduction P445: P46 P54x No Distance : M66 P841A: M66 Special All other products: M76 P443: M78B · Current Diff Starters for P 54x · Other improvements · Zone Q addition · PSB changes · VT input for Vn meas . ·...
Page 44: Features And Functions
Chapter 1 - Introduction P543i/P545i FEATURES AND FUNCTIONS CURRENT DIFFERENTIAL PROTECTION FUNCTIONS Feature IEC 61850 ANSI Phase segregated current differential protection DifPDIF1 Neutral current differential protection (optional) DifPDIF2 2 and 3 terminal lines/cables Feeders with in-zone transformers Suitable for use with SDH/SONET networks (using P594) GPS time synchronization (optional) DISTANCE PROTECTION FUNCTIONS Feature...
Page 45: Control Functions
P543i/P545i Chapter 1 - Introduction Feature IEC 61850 ANSI Phase overcurrent , with optional directionality (4 stages) OcpPTOC/RDIR 50/51/67 Earth/Ground overcurrent stages, with optional directionality (4 EfdPTOC/RDIR 50N/51N/ 67N stages) Sensitive earth fault (SEF) (4 stages) SenPTOC/RDIR 50N/51N/67N High impedance restricted earth fault (REF) SenRefPDIF Transient Earth Fault Detection (TEFD) PTEF...
Page 46: Measurement Functions
Chapter 1 - Introduction P543i/P545i Feature IEC 61850 ANSI Fault locator RFLO MEASUREMENT FUNCTIONS Measurement Function IEC 61850 ANSI Measurement of all instantaneous & integrated values (Exact range of measurements depend on the device model) Disturbance recorder for waveform capture – specified in samples per cycle RDRE Fault Records Maintenance Records Event Records / Event logging...
Page 47: Logic Diagrams
P543i/P545i Chapter 1 - Introduction LOGIC DIAGRAMS This technical manual contains many logic diagrams, which should help to explain the functionality of the device. Although this manual has been designed to be as specific as possible to the chosen product, it may contain diagrams, which have elements applicable to other products.
Page 48: Figure 2: Key To Logic Diagrams
Chapter 1 - Introduction P543i/P545i Key: Energising Quantity AND gate & Internal Signal OR gate DDB Signal XOR gate Internal function NOT gate Setting cell Logic 0 Setting value Timer Hardcoded setting Pulse / Latch Measurement Cell SR Latch Internal Calculation SR Latch Reset Dominant Derived setting...
Page 49: Functional Overview
P543i/P545i Chapter 1 - Introduction FUNCTIONAL OVERVIEW This diagram is applicable to P543 and P545models. BUS 1 2 nd Remote Remote Local Disturbance Fault records comm. port comm. port Communication Record 61850 Measurements Self monitoring 50N/ 50/27 50/51 I/ V 67/46 TEFD* V ref...
Page 50 Chapter 1 - Introduction P543i/P545i P54x1i-TM-EN-1...
Page 51: Chapter 2 Safety Information
CHAPTER 2 SAFETY INFORMATION...
Page 52 Chapter 2 - Safety Information P543i/P545i P54x1i-TM-EN-1...
Page 53: Chapter Overview
P543i/P545i Chapter 2 - Safety Information CHAPTER OVERVIEW This chapter provides information about the safe handling of the equipment. The equipment must be properly installed and handled in order to maintain it in a safe condition and to keep personnel safe at all times. You must be familiar with information contained in this chapter before unpacking, installing, commissioning, or servicing the equipment.
Page 54: Health And Safety
Chapter 2 - Safety Information P543i/P545i HEALTH AND SAFETY Personnel associated with the equipment must be familiar with the contents of this Safety Information. When electrical equipment is in operation, dangerous voltages are present in certain parts of the equipment. Improper use of the equipment and failure to observe warning notices will endanger personnel.
Page 55: Symbols
P543i/P545i Chapter 2 - Safety Information SYMBOLS Throughout this manual you will come across the following symbols. You will also see these symbols on parts of the equipment. Caution: Refer to equipment documentation. Failure to do so could result in damage to the equipment Warning: Risk of electric shock...
Page 56: Installation, Commissioning And Servicing
Chapter 2 - Safety Information P543i/P545i INSTALLATION, COMMISSIONING AND SERVICING LIFTING HAZARDS Many injuries are caused by: Lifting heavy objects ● Lifting things incorrectly ● ● Pushing or pulling heavy objects Using the same muscles repetitively ● Plan carefully, identify any possible hazards and determine how best to move the product. Look at other ways of moving the load to avoid manual handling.
Page 57: Ul/Csa/Cul Requirements
P543i/P545i Chapter 2 - Safety Information Caution: NEVER look into optical fibres or optical output connections. Always use optical power meters to determine operation or signal level. Warning: Testing may leave capacitors charged to dangerous voltage levels. Discharge capacitors by rediucing test voltages to zero before disconnecting test leads. Caution: Operate the equipment within the specified electrical and environmental limits.
Page 58: Equipment Connections
Chapter 2 - Safety Information P543i/P545i Caution: Digital input circuits should be protected by a high rupture capacity NIT or TIA fuse with maximum rating of 16 A. for safety reasons, current transformer circuits must never be fused. Other circuits should be appropriately fused to protect the wire used. Caution: CTs must NOT be fused since open circuiting them may produce lethal hazardous voltages...
Page 59: Pre-Energisation Checklist
P543i/P545i Chapter 2 - Safety Information Caution: Use a locknut or similar mechanism to ensure the integrity of stud-connected PCTs. Caution: The recommended minimum PCT wire size is 2.5 mm² for countries whose mains supply is 230 V (e.g. Europe) and 3.3 mm² for countries whose mains supply is 110 V (e.g. North America).
Page 60: Upgrading/Servicing
Chapter 2 - Safety Information P543i/P545i Note: For most Alstom equipment with ring-terminal connections, the threaded terminal block for current transformer termination is automatically shorted if the module is removed. Therefore external shorting of the CTs may not be required. Check the equipment documentation and wiring diagrams first to see if this applies.
Page 61: Decommissioning And Disposal
P543i/P545i Chapter 2 - Safety Information DECOMMISSIONING AND DISPOSAL Caution: Before decommissioning, completely isolate the equipment power supplies (both poles of any dc supply). The auxiliary supply input may have capacitors in parallel, which may still be charged. To avoid electric shock, discharge the capacitors using the external terminals before decommissioning.
Page 62: Regulatory Compliance
Chapter 2 - Safety Information P543i/P545i REGULATORY COMPLIANCE Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file. EMC COMPLIANCE: 2014/30/EU The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformit assessment used to demonstrate compliance with the EMC directive.
Page 63 P543i/P545i Chapter 2 - Safety Information Where: 'II' Equipment Group: Industrial. '(2)G' High protection equipment category, for control of equipment in gas atmospheres in Zone 1 and 2. This equipment (with parentheses marking around the zone number) is not itself suitable for operation within a potentially explosive atmosphere.
Page 64 Chapter 2 - Safety Information P543i/P545i P54x1i-TM-EN-1...
Page 65: Chapter 3 Hardware Design
CHAPTER 3 HARDWARE DESIGN...
Page 66 Chapter 3 - Hardware Design P543i/P545i P54x1i-TM-EN-1...
Page 67: Chapter Overview
P543i/P545i Chapter 3 - Hardware Design CHAPTER OVERVIEW This chapter provides information about the product's hardware design. This chapter contains the following sections: Chapter Overview Hardware Architecture Mechanical Implementation Front Panel Rear Panel Boards and Modules P54x1i-TM-EN-1...
Page 68: Hardware Architecture
Chapter 3 - Hardware Design P543i/P545i HARDWARE ARCHITECTURE The main components comprising devices based on the Px4x platform are as follows: The housing, consisting of a front panel and connections at the rear ● The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface ●...
Page 69: Figure 5: Coprocessor Hardware Architecture
P543i/P545i Chapter 3 - Hardware Design FPGA Comms between main and coprocessor board SRAM Ch1 for current differential input Optional comms interface Ch2 for current differential input Optional coprocessor board V00249 Figure 5: Coprocessor hardware architecture P54x1i-TM-EN-1...
Page 70: Mechanical Implementation
Chapter 3 - Hardware Design P543i/P545i MECHANICAL IMPLEMENTATION All products based on the Px4x platform have common hardware architecture. The hardware is modular and consists of the following main parts: Case and terminal blocks ● Boards and modules ● Front panel ●...
Page 71: List Of Boards
P543i/P545i Chapter 3 - Hardware Design Case width (TE) Case width (mm) Case width (inches) 40TE 203.2 60TE 304.8 80TE 406.4 Note: Not all case sizes are available for all models. LIST OF BOARDS The product's hardware consists of several modules drawn from a standard range. The exact specification and number of hardware modules depends on the model number and variant.
Page 72 Chapter 3 - Hardware Design P543i/P545i Coprocessor board with fibre connections for current differential inputs + GPS Coprocessor board with dual fibre inputs + GPS input. P54x1i-TM-EN-1...
Page 73: Front Panel
P543i/P545i Chapter 3 - Hardware Design FRONT PANEL FRONT PANEL Depending on the exact model and chosen options, the product will be housed in either a 40TE, 60TE or 80TE case. By way of example, the following diagram shows the front panel of a typical 60TE unit. The front panels of the products based on 40TE and 80TE cases have a lot of commonality and differ only in the number of hotkeys and user-programmable LEDs.
Page 74: Keypad
Chapter 3 - Hardware Design P543i/P545i The bottom compartment contains: A compartment for a 1/2 AA size backup battery (used to back up the real time clock and event, fault, and ● disturbance records). A 9-pin female D-type front port for an EIA(RS)232 serial connection to a PC. ●...
Page 75: Front Parallel Port (Sk2)
P543i/P545i Chapter 3 - Hardware Design Note: The front serial port does not support automatic extraction of event and disturbance records, although this data can be accessed manually. 4.1.3.1 FRONT SERIAL PORT (SK1) CONNECTIONS The port pin-out follows the standard for Data Communication Equipment (DCE) device with the following pin connections on a 9-pin connector.
Page 76: Programable Leds
Chapter 3 - Hardware Design P543i/P545i 4.1.7 PROGRAMABLE LEDS The device has a number of programmable LEDs, which can be associated with PSL-generated signals. The programmable LEDs for most models are tri-colour and can be set to RED, YELLOW or GREEN. However the programmable LEDs for some models are single-colour (red) only.
Page 77: Rear Panel
P543i/P545i Chapter 3 - Hardware Design REAR PANEL The MiCOM Px40 series uses a modular construction. Most of the internal workings are on boards and modules which fit into slots. Some of the boards plug into terminal blocks, which are bolted onto the rear of the unit. However, some boards such as the communications boards have their own connectors.
Page 78: Figure 9: Terminal Block Types
Chapter 3 - Hardware Design P543i/P545i Figure 9: Terminal block types Note: Not all products use all types of terminal blocks. The product described in this manual may use one or more of the above types. P54x1i-TM-EN-1...
Page 79: Boards And Modules
P543i/P545i Chapter 3 - Hardware Design BOARDS AND MODULES Each product comprises a selection of PCBs (Printed Circuit Boards) and subassemblies, depending on the chosen configuration. PCBS A PCB typically consists of the components, a front connector for connecting into the main system parallel bus via a ribbon cable, and an interface to the rear.
Page 80: Main Processor Board
Chapter 3 - Hardware Design P543i/P545i The products in the Px40 series typically contain two sub-assemblies: The power supply assembly comprising: ● ○ A power supply board An output relay board ○ The input module comprising: ● One or more transformer boards, which contains the voltage and current transformers (partially or ○...
Page 81: Power Supply Board
P543i/P545i Chapter 3 - Hardware Design POWER SUPPLY BOARD Figure 12: Power supply board The power supply board provides power to the unit. One of three different configurations of the power supply board can be fitted to the unit. This is specified at the time of order and depends on the magnitude of the supply voltage that will be connected to it.
Page 82: Figure 13: Power Supply Assembly
Chapter 3 - Hardware Design P543i/P545i Figure 13: Power supply assembly The power supply outputs are used to provide isolated power supply rails to the various modules within the unit. Three voltage levels are used by the unit’s modules: 5.1 V for all of the digital circuits ●...
Page 83: Watchdog
P543i/P545i Chapter 3 - Hardware Design Figure 14: Power supply terminals 6.4.1 WATCHDOG The Watchdog contacts are also hosted on the power supply board. The Watchdog facility provides two output relay contacts, one normally open and one normally closed. These are used to indicate the health of the device and are driven by the main processor board, which continually monitors the hardware and software when the device is in service.
Page 84: Rear Serial Port
Chapter 3 - Hardware Design P543i/P545i Figure 15: Watchdog contact terminals 6.4.2 REAR SERIAL PORT The rear serial port (RP1) is housed on the power supply board. This is a three-terminal EIA(RS)485 serial communications port and is intended for use with a permanently wired connection to a remote control centre for SCADA communication.
Page 85: Input Module - 1 Transformer Board
P543i/P545i Chapter 3 - Hardware Design Figure 16: Rear serial port terminals An additional serial port with D-type presentation is available as an optional board, if required. INPUT MODULE - 1 TRANSFORMER BOARD Figure 17: Input module - 1 transformer board The input module consists of the main input board coupled together with an instrument transformer board.
Page 86: Input Module Circuit Description
Chapter 3 - Hardware Design P543i/P545i 6.5.1 INPUT MODULE CIRCUIT DESCRIPTION 8 digital inputs Optical Optical Isolator Isolator Noise Noise filter filter Parallel Bus Buffer Transformer board Serial Link Serial A/D Converter interface V00239 Figure 18: Input module schematic A/D Conversion The differential analogue inputs from the CT and VT transformers are presented to the main input board as shown.
Page 87: Transformer Board
P543i/P545i Chapter 3 - Hardware Design The opto-isolated logic inputs can be configured for the nominal battery voltage of the circuit for which they are a part, allowing different voltages for different circuits such as signalling and tripping. Note: The opto-input circuitry can be provided without the A/D circuitry as a separate board, which can provide supplementary opto-inputs.
Page 88: Input Board
Chapter 3 - Hardware Design P543i/P545i 6.5.3 INPUT BOARD Figure 20: Input board The input board is used to convert the analogue signals delivered by the current and voltage transformers into digital quantities used by the IED. This input board also has on-board opto-input circuitry, providing eight optically- isolated digital inputs and associated noise filtering and buffering.
Page 89: Standard Output Relay Board
P543i/P545i Chapter 3 - Hardware Design Terminal Number Opto-input Terminal 17 Common Terminal 18 Common STANDARD OUTPUT RELAY BOARD Figure 21: Standard output relay board - 8 contacts This output relay board has 8 relays with 6 Normally Open contacts and 2 Changeover contacts. The output relay board is provided together with the power supply board as a complete assembly, or independently for the purposes of relay output expansion.
Page 90: Irig-B Board
Chapter 3 - Hardware Design P543i/P545i Terminal Number Output Relay Terminal 11 Relay 6 NO Terminal 12 Relay 6 NO Terminal 13 Relay 7 changeover Terminal 14 Relay 7 changeover Terminal 15 Relay 7 common Terminal 16 Relay 8 changeover Terminal 17 Relay 8 changeover Terminal 18...
Page 91: Fibre Optic Board
P543i/P545i Chapter 3 - Hardware Design FIBRE OPTIC BOARD Figure 23: Fibre optic board This board provides an interface for communicating with a master station. This communication link can use all compatible protocols (Courier, IEC 60870-5-103, MODBUS and DNP 3.0). It is a fibre-optic alternative to the metallic RS485 port presented on the power supply terminal block.
Page 92: Rear Communication Board
Chapter 3 - Hardware Design P543i/P545i REAR COMMUNICATION BOARD Figure 24: Rear communication board The optional communications board containing the secondary communication ports provide two serial interfaces presented on 9 pin D-type connectors. These interfaces are known as SK4 and SK5. Both connectors are female connectors, but are configured as DTE ports.
Page 93 P543i/P545i Chapter 3 - Hardware Design This is a communications board that provides a standard 100-Base Ethernet interface. This board supports one electrical copper connection and one fibre-pair connection. There are several variants for this board as follows: 100 Mbps Ethernet board ●...
Page 94: Redundant Ethernet Board
Chapter 3 - Hardware Design P543i/P545i 6.11 REDUNDANT ETHERNET BOARD IRIG-B Link Fail Pin3 connector Pin 2 Pin 1 Link channel B Link channel A (green LED) (green LED) Activity channel Activity channel B A (yellow LED) (yellow LED) V01009 Figure 26: Redundant Ethernet board This board provides dual redundant Ethernet (supported by two fibre pairs) together with an IRIG-B interface for timing.
Page 95 P543i/P545i Chapter 3 - Hardware Design Link Fail Connector (Ethernet Board Watchdog Relay) Closed Open Link fail Channel 1 (A) Link ok Channel 1 (A) Link fail Channel 2 (B) Link ok Channel 2 (B) LEDs Function Flashing Green Link Link ok Link broken Yellow...
Page 96: Coprocessor Board
Chapter 3 - Hardware Design P543i/P545i 6.12 COPROCESSOR BOARD Figure 27: Fully populated Coprocessor board Note: The above figure shows a coprocessor complete with GPS input and 2 fibre-optic serial data interfaces, and is not necessarily representative of the product and model described in this manual. These interfaces will not be present on boards that do not require them.
Page 97 P543i/P545i Chapter 3 - Hardware Design If, for example, Device A is transmitting to Device B information about the value of its measured current, the information Device A is receiving from Device B about the current measured at the same time, may reach device B at a different time.
Page 98 Chapter 3 - Hardware Design P543i/P545i P54x1i-TM-EN-1...
Page 99: Chapter 4 Software Design
CHAPTER 4 SOFTWARE DESIGN...
Page 100 Chapter 4 - Software Design P543i/P545i P54x1i-TM-EN-1...
Page 101: Chapter Overview
P543i/P545i Chapter 4 - Software Design CHAPTER OVERVIEW This chapter describes the software design of the IED. This chapter contains the following sections: Chapter Overview Sofware Design Overview System Level Software Platform Software Protection and Control Functions P54x1i-TM-EN-1...
Page 102: Sofware Design Overview
Chapter 4 - Software Design P543i/P545i SOFWARE DESIGN OVERVIEW The device software can be conceptually categorized into several elements as follows: The system level software ● The platform software ● ● The protection and control software These elements are not distinguishable to the user, and the distinction is made purely for the purposes of explanation.
Page 103: System Level Software
P543i/P545i Chapter 4 - Software Design SYSTEM LEVEL SOFTWARE REAL TIME OPERATING SYSTEM The real-time operating system is used to schedule the processing of the various tasks. This ensures that they are processed in the time available and in the desired order of priority. The operating system also plays a part in controlling the communication between the software tasks, through the use of operating system messages.
Page 104: System Level Software Initialisation
Chapter 4 - Software Design P543i/P545i 3.4.2 SYSTEM LEVEL SOFTWARE INITIALISATION The initialization process initializes the processor registers and interrupts, starts the watchdog timers (used by the hardware to determine whether the software is still running), starts the real-time operating system and creates and starts the supervisor task.
Page 105 P543i/P545i Chapter 4 - Software Design If the problem is with the battery status or the IRIG-B board, the device continues in operation. For problems detected in any other area, the device initiates a shutdown and re-boot, resulting in a period of up to 10 seconds when the functionality is unavailable.
Page 106: Platform Software
Chapter 4 - Software Design P543i/P545i PLATFORM SOFTWARE The platform software has three main functions: To control the logging of records generated by the protection software, including alarms, events, faults, and ● maintenance records To store and maintain a database of all of the settings in non-volatile memory ●...
Page 107: Protection And Control Functions
P543i/P545i Chapter 4 - Software Design PROTECTION AND CONTROL FUNCTIONS The protection and control software processes all of the protection elements and measurement functions. To achieve this it has to communicate with the system services software, the platform software as well as organise its own operations.
Page 108: Distance Protection
Chapter 4 - Software Design P543i/P545i board and converts these to 8 samples per cycle based on the nominal frequency. The coprocessor calculates the Fourier transform of the fixed rate samples after every sample, using a one-cycle window. This generates current measurements eight times per cycle which are used for the differential protection algorithm.
Page 109: Programmable Scheme Logic
P543i/P545i Chapter 4 - Software Design The Fourier function acts as a filter, with zero gain at DC and unity gain at the fundamental, but with good harmonic rejection for all harmonic frequencies up to the nyquist frequency. Frequencies beyond this nyquist frequency are known as alias frequencies, which are introduced when the sampling frequency becomes less than twice the frequency component being sampled.
Page 110: Event Recording
Chapter 4 - Software Design P543i/P545i EVENT RECORDING A change in any digital input signal or protection element output signal is used to indicate that an event has taken place. When this happens, the protection and control task sends a message to the supervisor task to indicate that an event is available to be processed and writes the event data to a fast buffer controlled by the supervisor task.
Page 111: Chapter 5 Configuration
CHAPTER 5 CONFIGURATION...
Page 112 Chapter 5 - Configuration P543i/P545i P54x1i-TM-EN-1...
Page 113: Chapter Overview
P543i/P545i Chapter 5 - Configuration CHAPTER OVERVIEW Each product has different configuration parameters according to the functions it has been designed to perform. There is, however, a common methodology used across the entire product series to set these parameters. Some of the communications setup can only be carried out using the HMI, and cannot be carried out using settings applications software.
Page 114: Settings Application Software
Chapter 5 - Configuration P543i/P545i SETTINGS APPLICATION SOFTWARE To configure this device you will need to use the Settings Application Software. The settings application software used in this range of IEDs is called MiCOM S1 Agile. It is a collection of software tools, which is used for setting up and managing the IEDs.
Page 115: Using The Hmi Panel
P543i/P545i Chapter 5 - Configuration USING THE HMI PANEL Using the HMI, you can: Display and modify settings ● View the digital I/O signal status ● ● Display measurements Display fault records ● Reset fault and alarm indications ● The keypad provides full access to the device functionality using a range of menu options. The information is displayed on the LCD.
Page 116: Figure 31: Navigating The Hmi
Chapter 5 - Configuration P543i/P545i Note: As the LCD display has a resolution of 16 characters by 3 lines, some of the information is in a condensed mnemonic form. NAVIGATING THE HMI PANEL The cursor keys are used to navigate the menus. These keys have an auto-repeat function if held down continuously.
Page 117: Default Display
P543i/P545i Chapter 5 - Configuration If there are alarms present, the yellow Alarms LED will be flashing and the menu display will read as follows: Alarms / Faults Present HOTKEY Even though the device itself should be in full working order when you first start it, an alarm could still be present, for example, if there is no network connection for a device fitted with a network card.
Page 118: Figure 32: Default Display Navigation
Chapter 5 - Configuration P543i/P545i Plant reference (user-defined) For example: Plant Reference MiCOM HOTKEY Access Level For example: Access Level HOTKEY In addition to the above, there are also displays for the system voltages, currents, power and frequency etc., depending on the device model. DEFAULT DISPLAY NAVIGATION The following diagram is an example of the default display navigation.
Page 119: Password Entry
P543i/P545i Chapter 5 - Configuration If the device is cyber-secure but is not yet configured for NERC compliance (see Cyber-security chapter), a warning will appear when moving from the "NERC compliant" banner. The warning message is as follows: DISPLAY NOT NERC COMPLIANT.
Page 120: Menu Structure
Chapter 5 - Configuration P543i/P545i Press Clear To Reset Alarms To clear all alarm messages, press the Clear key. To return to the display showing alarms or faults present, and leave the alarms uncleared, press the Read key. Depending on the password configuration settings, you may need to enter a password before the alarm messages can be cleared.
Page 121: Changing The Settings
P543i/P545i Chapter 5 - Configuration Setting Column Description Sys Fn Links (Row 03) Third setting within first column … … … VIEW RECORDS Second Column definition Select Event [0...n] First setting within second column Menu Cell Ref Second setting within second column Time &...
Page 122: Direct Access (The Hotkey Menu)
Chapter 5 - Configuration P543i/P545i Note: For the protection group and disturbance recorder settings, if the menu time-out occurs before the changes have been confirmed, the setting values are discarded. Control and support settings, howeverr, are updated immediately after they are entered, without the Update settings? prompt.
Page 123: Circuit Breaker Control
P543i/P545i Chapter 5 - Configuration To access the hotkey menu from the default display, you press the key directly below the HOTKEY text on the LCD. The following screen will appear. ¬User32 STG GP® HOTKEY MENU EXIT Press the right cursor key twice to get to the first control input, or the left cursor key to get to the last control input. ¬STP GP User02®...
Page 124 Chapter 5 - Configuration P543i/P545i The first cell down in the FUNCTION KEYS column is the Fn Key Status cell. This contains a binary string, which represents the function key commands. Their status can be read from this binary string. FUNCTION KEYS Fn Key Status 0000000000...
Page 125: Figure 33: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
P543i/P545i Chapter 5 - Configuration LINE PARAMETERS This product requires information about the circuit to which it is applied. This includes line impedance, residual compensation, and phase rotation sequence. For this reason circuit parameter information must be input using the LINE PARAMETERS settings. These LINE PARAMETERS settings are used by protection elements as well as by the fault locator.
Page 126: Residual Compensation
Chapter 5 - Configuration P543i/P545i RESIDUAL COMPENSATION To improve accuracy of impedance measuring elements such as those used in distance protection and fault locators, the total loop impedance calculation Z can be calibrated by the positive sequence impedance between the relaying point and the fault (Z ) using the following equation: ⋅...
Page 127 P543i/P545i Chapter 5 - Configuration is the residual current of the parallel line (measured) ● ● is the residual compensation coefficient is the mutual compensation coefficient ● In the above equation: − where: is the total zero sequence impedance of the line (a complex value) ●...
Page 128: Date And Time Configuration
Chapter 5 - Configuration P543i/P545i DATE AND TIME CONFIGURATION The date and time setting will normally be updated automatically by the chosen UTC (Universal Time Co- ordination) time synchronisation mechanism when the device is in service. You can also set the date and time manually using the Date/Time cell in the DATE AND TIME column.
Page 129: Without A Timing Source Signal
P543i/P545i Chapter 5 - Configuration Ensure that the IED is receiving valid time synchronisation messages by checking that the PTP Status cell reads Valid Master. Check that Act. Time Source cell reads PTP. This indicates that the IED is using PTP as the source for its time.
Page 130: Daylight Saving Time Compensation
Chapter 5 - Configuration P543i/P545i DAYLIGHT SAVING TIME COMPENSATION It is possible to compensate for Daylight Saving time using the following settings DST Enable ● ● DST Offset DST Start ● ● DST Start Day DST Start Month ● DST Start Mins ●...
Page 131: Settings Group Selection
P543i/P545i Chapter 5 - Configuration SETTINGS GROUP SELECTION You can select the setting group using opto inputs, a menu selection, and for some models the hotkey menu or function keys. You choose which method using the Setting Group setting in the CONFIGURATION column. There are two possibilities;...
Page 132 Chapter 5 - Configuration P543i/P545i P54x1i-TM-EN-1...
Page 133: Chapter 6 Current Differential Protection
CHAPTER 6 CURRENT DIFFERENTIAL PROTECTION...
Page 134 Chapter 6 - Current Differential Protection P543i/P545i P54x1i-TM-EN-1...
Page 135: Chapter Overview
P543i/P545i Chapter 6 - Current Differential Protection CHAPTER OVERVIEW This product provides biased, phase-segregated, numerical Current Differential protection. This chapter introduces the principles and theory behind Current Differential protection and describes how they are implemented in this product. Guidance for applying this protection is also provided. The current differential protection is enabled by default, but it can be disabled if you don’t want to use it.
Page 136: Current Differential Protection Principle
Chapter 6 - Current Differential Protection P543i/P545i CURRENT DIFFERENTIAL PROTECTION PRINCIPLE Current differential protection is based on Kirchoff’s Law. It generally uses the Merz-Price principle in which the sum of the currents entering the protected zone should equal the sum of the currents leaving the protected zone. A difference between these currents is known as differential current.
Page 137 P543i/P545i Chapter 6 - Current Differential Protection applications use three current values (one from each terminal) for the evaluation of the Bias and Differential currents. Line differential protection requires the comparison of power system quantities taken at the different line terminals.
Page 138: Figure 34: Ping-Pong Measurement For Alignment Of Current Signals
Chapter 6 - Current Differential Protection P543i/P545i SYNCHRONISATION OF CURRENT SIGNALS To ensure accuracy of the calculation of the differential current, the locally derived current values and the values derived from inputs at remote terminals must be aligned to a common time reference before the differential calculations are made.
Page 139: Gps Synchronisation
P543i/P545i Chapter 6 - Current Differential Protection At time tA1, End A sends a data message to End B. The message contains a time tag, tA1, plus other timing, control, and status information as well as the calculated current values. The message arrives at End B after a channel after a propogation delay time tp1.
Page 140: Figure 35: Asymmetric Propogation Delay Times
Chapter 6 - Current Differential Protection P543i/P545i tp 1 tB3* tp 2 Relay A Relay B E02607 Figure 35: Asymmetric propogation delay times The GPS synchronised values at terminal A (tA1, etc.) can be individually compared with those at terminal B (tB1, etc.) to derive the bias and differential currents.
Page 141: Figure 36: Dual Slope Current Differential Bias Characteristic
P543i/P545i Chapter 6 - Current Differential Protection PHASE CURRENT DIFFERENTIAL PROTECTION By appropriate model selection, current differential protection can be provided for two-terminal or three-terminal feeders. Products that have two protection communications channels fitted can be applied to the protection of three-terminal applications.
Page 142: Phase Current Differential Tripping Criteria
Chapter 6 - Current Differential Protection P543i/P545i PHASE CURRENT DIFFERENTIAL TRIPPING CRITERIA The phase current differential characteristic is defined by four settings: Phase Is1: The basic differential current setting which determines the minimum pick-up level of the ● protection. Phase k1: The lower percentage bias setting used when the bias current is below the Phase Is2 setting. This ●...
Page 143: Figure 37: Phase Current Differential Protection Logic
P543i/P545i Chapter 6 - Current Differential Protection PHASE CURRENT DIFFERENTIAL PROTECTION LOGIC Permit Cdiff Diff Trip IDiff>Start A & Phase A Operate threshold & Diff Trip A reached Send Diff Intertrip A IDiff>Start B & Phase B Operate threshold & Diff Trip B reached Send Diff Intertrip B...
Page 144: Neutral Current Differential Protection
Chapter 6 - Current Differential Protection P543i/P545i NEUTRAL CURRENT DIFFERENTIAL PROTECTION In products that feature distance back-up protection, Neutral Current Differential protection is provided to clear high-resistive earth faults which may be below the Phase Current Differential sensitivity limit. If you wish to use the Neutral Current Differential protection you must enable it using the In Diff setting under the NEUTRAL DIFF subheading of the CURRENT DIFF column.
Page 145: Three-Terminal Schemes
P543i/P545i Chapter 6 - Current Differential Protection THREE-TERMINAL SCHEMES Products that have two protection communications channels fitted can be applied to the protection of three- terminal applications. By appropriate model selection, current differential protection can be provided for two-terminal or three-terminal feeders.
Page 146: Three-Terminal Scheme Reconfiguration On Energisation
Chapter 6 - Current Differential Protection P543i/P545i If the current configuration is Two-Ended and the new setting is Three-Ended, the device checks that all the communications are healthy and sends out the restore command to the other devices. It then checks that the scheme has stabilised as ‘Three-Ended’...
Page 147: Transient Bias
P543i/P545i Chapter 6 - Current Differential Protection TRANSIENT BIAS Phase current differential protection stability for current transformers is assisted by a feature called Transient Bias. This can be enabled or disabled with the transient Bias setting in the CURRENT DIFF column. Saturation of current transformers (CTs) under heavy load or external fault conditions can cause the protection to see differential current and could lead to tripping.
Page 148: Figure 38: Capacitive Charging Current
Chapter 6 - Current Differential Protection P543i/P545i CAPACITIVE CHARGING CURRENT COMPENSATION All electrical conductors, including feeders, are capacitively coupled to earth. When energised, a capacitive current flows from the feeder to earth to charge the capacitance. The capacitance is distributed along the feeder, but for analysis it can be modelled according with the following figure.
Page 149: Figure 39: Ct Compensation
P543i/P545i Chapter 6 - Current Differential Protection CT COMPENSATION The primary and secondary ratios for the phase current transformers are set in the CT AND VT RATIOS column. These settings are used to display the phase current quantities in the MEASUREMENTS 1 column. The device can be set to display the input current either in primary values or in secondary values.
Page 150: Feeders With In-Zone Transformers
Chapter 6 - Current Differential Protection P543i/P545i FEEDERS WITH IN-ZONE TRANSFORMERS A transformer feeder comprises a transformer directly connected to a transmission circuit without the intervention of switchgear. Although separate current transformer inputs may be available to allow separate overlapping zones of protection for the transformer and the feeder this is not always the case and the transformer and the feeder must be treated and protected as a single item of plant for protection.
Page 151: Zero Sequence Filtering
P543i/P545i Chapter 6 - Current Differential Protection Setting Phase shift Action 180 lag Invert currents 150 lead Yd1 and Invert Ia = IC 120 lead Ib = IA Ic = IB 90 lead Yd3 and Invert Ia = -IB Yy10 60 lead Ib = -IC Ic = -IA...
Page 152: Figure 40: The Need For Zero-Sequence Current Filtering
Chapter 6 - Current Differential Protection P543i/P545i IED1 IED2 Digital communication channel IED1 IED2 Received Received diff diff E02611 Figure 40: The need for zero-sequence current filtering Where a transformer winding can pass zero sequence current to an external earth fault, it is essential that some form of zero sequence current filtering is used.
Page 153: Figure 41: Magnetising Inrush Phenomenon
P543i/P545i Chapter 6 - Current Differential Protection Steady state Switch on at voltage zero – No residual flux V = Voltage, F = Flux, Im = magnetising current, Fm = maximum flux V03123 Figure 41: Magnetising inrush phenomenon The main characteristics of magnetising inrush currents are: ●...
Page 154 Chapter 6 - Current Differential Protection P543i/P545i Using the Inrush Restraint setting you can choose what will happen to differential characteristic in the presence of second harmonic current: If set to Disabled, the characteristic will not be modified, ● If set to Restraint, the characteristic will be restrained if the second harmonic component is above a ●...
Page 155: Figure 42: Typical Overflux Current Waveform
P543i/P545i Chapter 6 - Current Differential Protection remain stable for magnetising inrush conditions, but to operate for internal faults. To discriminate between the two, an unrestrained high set differential protection is included. If Inrush Restraint is set either to Restraint or to Blocking, an unrestrained high set differential protection becomes visible.
Page 156: Figure 43: Phase Current Differential Protection Logic For Feeders With In-Zone Transformers
Chapter 6 - Current Differential Protection P543i/P545i 10.5 LOGIC FOR FEEDERS WITH IN-ZONE TRANSFORMERS Permit Cdiff & Phase A Operate LS & IDiff>Start A threshold reached & Phase A Operate HS & IDiff>>Start A threshold reached & Phase B Operate LS &...
Page 157: Figure 44: Second Harmonic Blocking Logic
P543i/P545i Chapter 6 - Current Differential Protection 10.6 SECOND HARMONIC BLOCKING LOGIC Phase A 2 harmonic threshold reached & Ih(2) Loc Blk A Ih(2) Loc Blk A** Phase B 2 harmonic threshold reached & Ih(2) Loc Blk B Ih(2) Loc Blk B** Phase C 2 harmonic threshold reached...
Page 158: Figure 45: Fifth Harmonic Blocking Logic
Chapter 6 - Current Differential Protection P543i/P545i 10.7 FIFTH HARMONIC BLOCKING LOGIC Phase A 5 harmonic threshold reached & Ih(5) Loc Blk A Ih(5) Loc Blk A** Phase B 5 harmonic threshold reached & Ih(5) Loc Blk B Ih(2) Loc Blk B** Phase C 5 harmonic threshold reached...
Page 159: Figure 46: Permissive Intertripping Example
P543i/P545i Chapter 6 - Current Differential Protection CURRENT DIFFERENTIAL INTERTRIPPING Eight freely assignable intertripping signals are provided by a facility called InterMICOM64, which is described in the chapter on Fibre Teleprotection. In addition there are two intertripping functions associated directly with the Current Differential protection.
Page 160: Figure 47: Stub Bus Protection
Chapter 6 - Current Differential Protection P543i/P545i STUB BUS DIFFERENTIAL PROTECTION This product can provide stub-bus protection associated with the differential protection. If you wish to use this feature you must ensure that the current differential protection is enabled. You will need to map one of the opto-isolated inputs to the DDB Stub Bus Enabled using the programmable scheme logic and you will need to enable the feature by setting Ph Diff Stub Bus in the CURRENT DIFF column to Enabled.
Page 161: Application Notes
P543i/P545i Chapter 6 - Current Differential Protection APPLICATION NOTES 13.1 SETTING UP THE PHASE DIFFERENTIAL CHARACTERISTIC The biased phase current differential characteristic is defined by four protection settings. Each can be set independently. This flexibility allows the characteristic to be set for particular sensitivity and current transformer requirements.
Page 162: Sensitivity Under Heavy Loads
Chapter 6 - Current Differential Protection P543i/P545i If there is a mismatch between CTs at line ends, then the lowest primary CT rated current should be used as a reference current for p.u. calculations (assuming that the load current cannot continuously exceed this value). This means that the recommended settings Phase Is1 = 0.2 pu is equal to 0.2*(the lowest primary CT rated value).
Page 163: Permissive Intertripping
P543i/P545i Chapter 6 - Current Differential Protection | = (Vph-n /R )(1/CT ratio) pu = 47.63/R Based on the analysis above, the phase current differential protection detects a fault current in excess of 0.59 pu with a load current of 1 pu flowing. The fault resistance is less than 47.63/0.59 = 81 ohms in this case. With a short time overload current of 2.0 pu, the phase current differential protection can detect a fault resistance of 47.63/1.6 = 30 ohms or lower.
Page 164: Feeders With Small Tapped Loads
Chapter 6 - Current Differential Protection P543i/P545i Setting End X End Y End Z Phase Is1 (Primary) 0.5*500 = 250A 0.5*800 = 400A 0.5*200 = 100A Phase Is1 (Secondary) 0.5*5 = 2.5A 0.5*5 = 2.5A 0.5*1 = 0.5A Phase Is2 [p.u.] 1000/200 = 5 1000/200 = 5 1000/200 = 5...
Page 165: Figure 48: Typical Two-Terminal Plain Feeder Circuit
P543i/P545i Chapter 6 - Current Differential Protection 33 kV 33 kV 400/1 400/1 25 km Protected line Digital communication link P54x P54x Steady state charging current = 2.5 A/km – cable = 0.1 A/km – overhead line V02621 Figure 48: Typical two-terminal plain feeder circuit In the case that voltage inputs are not in place, no facility to account for line charging current is available.
Page 166: Figure 49: Typical Three-Terminal Plain Feeder Circuit
Chapter 6 - Current Differential Protection P543i/P545i These settings will give a characteristic suitable for most applications. It leaves only the Phase Is1 setting to be decided by you. The value of this setting should be in excess of any mismatch between line ends. It should also account for line charging current, where necessary.
Page 167 P543i/P545i Chapter 6 - Current Differential Protection Phase k1 = 30% Phase k2 = 100% Therefore, settings in primary/secondary values for each device can be calculated as follows: Setting End A End B End C Phase CT Primary 4000A 4000A 1200A Phase CT Sec’y Phase Is1 [p.u.]...
Page 168 Chapter 6 - Current Differential Protection P543i/P545i P54x1i-TM-EN-1...
Page 169: Chapter 7 Distance Protection
CHAPTER 7 DISTANCE PROTECTION...
Page 170 Chapter 7 - Distance Protection P543i/P545i P54x1i-TM-EN-1...
Page 171: Chapter Overview
P543i/P545i Chapter 7 - Distance Protection CHAPTER OVERVIEW This chapter introduces the principles and theory behind the protection and describes how it is implemented in this product. Guidance for applying this protection is also provided. This chapter contains the following sections: Chapter Overview Introduction Distance Measuring Zones Operating Principles...
Page 172: Figure 50: System Impedance Ratio
Chapter 7 - Distance Protection P543i/P545i INTRODUCTION Amongst protection engineers, the basic principles of Distance Protection are widely documented and understood. If you are reading this chapter, we assume that you are familiar with the principles of distance protection and associated components such as Aided Schemes.
Page 173: Impedance Calculation
P543i/P545i Chapter 7 - Distance Protection where SIR = Z From the equation above, it can be seen that the measured voltage has a significant impact on the decision making process. The ability of distance protection to measure accurately for a given reach point fault, depends on the voltage at the relaying location being above a minimum value at the time of the fault.
Page 174: Distance Measuring Zones Operating Principles
Chapter 7 - Distance Protection P543i/P545i DISTANCE MEASURING ZONES OPERATING PRINCIPLES All distance zone characteristics in this product are constructed with one or more comparators. The comparators are used to construct either Mho, or Quadrilateral characteristics. This section outlines the principles behind the construction of the characteristics in order to provide an understanding of how best to set them.
Page 175: Figure 51: Directional Mho Element Construction
P543i/P545i Chapter 7 - Distance Protection Note: The faulted phase current (I) is generally used as the reference (0º) for the vector diagrams. MHO CHARACTERISTICS There are different types of Mho characteristic, but two specific ones are well suited to introducing the defining principles.
Page 176: Figure 52: Offset Mho Characteristic
Chapter 7 - Distance Protection P543i/P545i   I  90°      V02711 Figure 52: Offset Mho characteristic The two signals provided to the comparator are: = V - IZ' = V - IZ Operation occurs when the angle between the signals is greater than 90° 3.1.3 DIRECTIONAL SELF-POLARIZED MHO CHARACTERISTIC FOR EARTH FAULTS Characteristics of earth-fault elements can be represented in two different complex planes - the positive sequence...
Page 177: Figure 53: Directional Mho Element Construction - Impedance Domain
P543i/P545i Chapter 7 - Distance Protection Plane Plane   j    replica  replica 90° 90°   V02712 Figure 53: Directional Mho element construction – impedance domain The two signals provided to the comparator are: = V - IZ where (for an A-N fault for example) with residual compensation applied: V = V I = I...
Page 178: Figure 54: Offset Mho Characteristics - Impedance Domain
Chapter 7 - Distance Protection P543i/P545i Z(1+k Then if healthy phase currents are much less then the current of the faulty phase and the mutual compensation is disabled: so that @ Z(1 + k replica Thus the Z plane representation of the characteristic becomes static. 3.1.4 OFFSET MHO CHARACTERISTIC FOR EARTH FAULTS The diagram below illustrates how the Offset Mho characteristic for earth-fault distance protection is created in...
Page 179: Figure 55: Offset Mho Characteristics - Voltage Domain
P543i/P545i Chapter 7 - Distance Protection -plane     replica replica 90°  Z  replica Z    replica    V02714 Figure 55: Offset mho characteristics – voltage domain where: Z is the replica forward reach and Z' is the replica reverse reach.
Page 180: Figure 56: Simplified Forward Fault
Chapter 7 - Distance Protection P543i/P545i 3.1.5 MEMORY POLARIZATION OF MHO CHARACTERISTICS Self-Polarized Directional Mho characteristics require sufficient polarizing voltage to detect the voltage angle. Therefore such a characteristic is unable to operate for close-up faults where there would be insufficient polarizing voltage.
Page 181: Figure 57: Mho Expansion - Forward Fault
P543i/P545i Chapter 7 - Distance Protection  Self-polarised  90°        V02716 Figure 57: Mho expansion – forward fault The Mho expansion associated with forward faults is as follows: Mho Expansion = Z p/(1 +p) where Z is the impedance of the source behind the relaying point.
Page 182: Figure 58: Simplified Reverse Fault
Chapter 7 - Distance Protection P543i/P545i Dist Network V02717 Figure 58: Simplified Reverse Fault For a fault condition we can write the following equations: = V - I(Z   V I Z ° ≤ ∠ − ⋅  − ∠ −...
Page 183: Figure 59: Mho Contraction - Reverse Fault
P543i/P545i Chapter 7 - Distance Protection      90°   Z    Self-polarised V02718 Figure 59: Mho contraction – reverse fault The Mho contraction associated with reverse faults is as follows: Mho Contraction = (Z ).p/(1 + p) where Z is the impedance of the line and the source ahead of the

GE MiCOM P40 Agile Technical Manual

Quick Links

3 Table of Contents

27 Table of Figures

37 Chapter 1 Introduction

39 Section 3

51 Chapter 2 Safety Information

65 Chapter 3 Hardware Design

67 Section 4

99 Chapter 4 Software Design

101 Section 5

111 Chapter 5 Configuration

113 Section 6

133 Chapter 6 Current Differential Protection

135 Section 7

169 Chapter 7 Distance Protection

243 Chapter 8 Carrier Aided Schemes

287 Chapter 9 Non-Aided Schemes

Chapters

3 Table of Contents

27 Table of Figures

37 Chapter 1 Introduction

39 Section 3

51 Chapter 2 Safety Information

65 Chapter 3 Hardware Design

67 Section 4

99 Chapter 4 Software Design

101 Section 5

111 Chapter 5 Configuration

113 Section 6

133 Chapter 6 Current Differential Protection

135 Section 7

169 Chapter 7 Distance Protection

243 Chapter 8 Carrier Aided Schemes

287 Chapter 9 Non-Aided Schemes

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Summary of Contents for GE MiCOM P40 Agile

3
Table of Contents

27
Table of Figures

37
Chapter 1 Introduction

39
Section 3

51
Chapter 2 Safety Information

65
Chapter 3 Hardware Design

67
Section 4

99
Chapter 4 Software Design

101
Section 5

111
Chapter 5 Configuration

113
Section 6

133
Chapter 6 Current Differential Protection

135
Section 7

169
Chapter 7 Distance Protection

243
Chapter 8 Carrier Aided Schemes

287
Chapter 9 Non-Aided Schemes

3
Table of Contents

27
Table of Figures

37
Chapter 1 Introduction

39
Section 3

51
Chapter 2 Safety Information

65
Chapter 3 Hardware Design

67
Section 4

99
Chapter 4 Software Design

101
Section 5

111
Chapter 5 Configuration

113
Section 6

133
Chapter 6 Current Differential Protection

135
Section 7

169
Chapter 7 Distance Protection

243
Chapter 8 Carrier Aided Schemes

287
Chapter 9 Non-Aided Schemes