GE MiCOM P40 Agile Technical Manual

37

Chapter 1 Introduction

• 39

  Chapter Overview
• 40

  Foreword
• 40

  Target Audience
• 40

  Typographical Conventions
• 41

  Compliance
• 41

  Nomenclature
• 42

  Product Scope
• 42

  Product Versions
• 43

  Figure 1: P40L Version M85 - Version Evolution
• 43

  Ordering Options
• 44

  Current Differential Protection Functions
• 44

  Distance Protection Functions
• 44

  Features and Functions
• 44

  Protection Functions
• 45

  Control Functions
• 46

  Communication Functions
• 46

  Measurement Functions
• 47

  Logic Diagrams
• 48

  Figure 2: Key to Logic Diagrams
• 49

  Figure 3: Functional Overview
• 49

  Functional Overview

51

Chapter 2 Safety Information

• 53

  Chapter Overview
• 54

  Health and Safety
• 55

  Symbols
• 56

  Installation, Commissioning and Servicing
• 56

  Lifting Hazards
• 56

  Electrical Hazards
• 57

  UL/CSA/CUL Requirements
• 57

  Fusing Requirements
• 58

  Equipment Connections
• 58

  Protection Class 1 Equipment Requirements
• 59

  Pre-Energisation Checklist
• 59

  Peripheral Circuitry
• 60

  Upgrading/Servicing
• 61

  Decommissioning and Disposal
• 62

  Regulatory Compliance
• 62

  EMC Compliance: 2014/30/EU
• 62

  LVD Compliance: 2014/35/EU
• 62

  R&TTE Compliance: 2014/53/EU
• 62

  UL/CUL Compliance
• 62

  ATEX Compliance: 2014/34/EU

65

Chapter 3 Hardware Design

• 67

  Chapter Overview
• 68

  Coprocessor Hardware Architecture
• 68

  Figure 4: Hardware Architecture
• 68

  Hardware Architecture
• 69

  Figure 5: Coprocessor Hardware Architecture
• 70

  Figure 6: Exploded View of IED
• 70

  Housing Variants
• 70

  Mechanical Implementation
• 71

  List of Boards
• 73

  Front Panel
  • 73

    Front Panel Compartments
  • 73

    Figure 7: Front Panel (60TE)
  • 74

    Keypad
  • 74

    Front Serial Port (SK1)
  • 75

    Front Parallel Port (SK2)
  • 75

    Fixed Function Leds
  • 75

    Function Keys
  • 76

    Programable Leds
• 77

  Figure 8: Rear View of Populated Case
• 77

  Rear Panel
• 78

  Figure 9: Terminal Block Types
• 79

  Boards and Modules
• 79

  Figure 10: Rear Connection to Terminal Block
• 79

  Pcbs
• 79

  Subassemblies
• 80

  Figure 11: Main Processor Board
• 80

  Main Processor Board
• 81

  Figure 12: Power Supply Board
• 81

  Power Supply Board
• 82

  Figure 13: Power Supply Assembly
  • 83

    Watchdog
  • 83

    Figure 14: Power Supply Terminals
  • 84

    Rear Serial Port
  • 84

    Figure 15: Watchdog Contact Terminals
• 85

  Figure 16: Rear Serial Port Terminals
• 85

  Figure 17: Input Module - 1 Transformer Board
  • 86

    Input Module Circuit Description
  • 86

    Figure 18: Input Module Schematic
  • 87

    Transformer Board
  • 87

    Figure 19: Transformer Board
  • 88

    Input Board
  • 88

    Figure 20: Input Board
• 85

  Input Module - 1 Transformer Board
• 89

  Figure 21: Standard Output Relay Board - 8 Contacts
• 89

  Standard Output Relay Board
• 90

  Figure 22: IRIG-B Board
• 90

  IRIG-B Board
• 91

  Fibre Optic Board
• 91

  Figure 23: Fibre Optic Board
• 92

  Ethernet Board
• 92

  Figure 24: Rear Communication Board
• 92

  Figure 25: Ethernet Board
• 92

  Rear Communication Board
• 94

  Figure 26: Redundant Ethernet Board
• 94

  Redundant Ethernet Board
• 96

  Coprocessor Board
• 96

  Coprocessor Board With 1PPS Input
• 96

  Current Differential Inputs
• 96

  Figure 27: Fully Populated Coprocessor Board

99

Chapter 4 Software Design

• 101

  Chapter Overview
• 102

  Figure 28: Software Architecture
• 102

  Sofware Design Overview
• 103

  Real Time Operating System
• 103

  Self-Diagnostic Software
• 103

  Startup Self-Testing
  • 103

    System Boot
  • 104

    System Level Software Initialisation
  • 104

    Platform Software Initialisation and Monitoring
• 103

  System Level Software
• 103

  System Services Software
• 104

  Continuous Self-Testing
• 106

  Interfaces
• 106

  Platform Software
• 106

  Record Logging
• 106

  Settings Database
• 107

  Acquisition of Samples
• 107

  Direct Use of Sample Values
• 107

  Frequency Tracking
• 107

  Protection and Control Functions
• 107

  System Level Software Initialisation
• 108

  Distance Protection
• 108

  Figure 29: Frequency Response of FIR Filters
• 108

  Fourier Signal Processing
• 109

  Figure 30: Frequency Response (Indicative Only)
• 109

  Programmable Scheme Logic
• 110

  Disturbance Recorder
• 110

  Event Recording
• 110

  Fault Locator

111

Chapter 5 Configuration

• 113

  Chapter Overview
• 114

  Settings Application Software
• 115

  Using the HMI Panel
• 116

  Figure 31: Navigating the HMI
• 117

  Default Display
• 118

  Figure 32: Default Display Navigation
• 119

  Password Entry
• 120

  Menu Structure
• 121

  Changing the Settings
• 122

  Direct Access (The Hotkey Menu)
• 123

  Circuit Breaker Control
• 125

  Figure 33: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
• 125

  Line Parameters
• 126

  Residual Compensation
  • 128

    Date and Time Configuration
  • 129

    Without a Timing Source Signal
  • 130

    Daylight Saving Time Compensation
  • 131

    Settings Group Selection

133

Chapter 6 Current Differential Protection

• 135

  Chapter Overview
• 136

  Current Differential Protection Principle
• 138

  Figure 34: Ping-Pong Measurement for Alignment of Current Signals
• 138

  Synchronisation of Current Signals
• 139

  GPS Synchronisation
• 140

  Figure 35: Asymmetric Propogation Delay Times
• 141

  Figure 36: Dual Slope Current Differential Bias Characteristic
• 141

  Phase Current Differential Protection
• 142

  Phase Current Differential Tripping Criteria
• 143

  Figure 37: Phase Current Differential Protection Logic
• 144

  Neutral Current Differential Protection
• 145

  Three-Terminal Schemes
• 146

  Three-Terminal Scheme Reconfiguration On Energisation
• 147

  Transient Bias
• 148

  Capacitive Charging Current Compensation
• 148

  Figure 38: Capacitive Charging Current
• 149

  CT Compensation
• 149

  Figure 39: CT Compensation
• 150

  Feeders With In-Zone Transformers
• 151

  Zero Sequence Filtering
• 152

  Figure 40: the Need for Zero-Sequence Current Filtering
• 152

  Magnetising Inrush Restraint
• 153

  Figure 41: Magnetising Inrush Phenomenon
• 153

  Second Harmonic Restraint
• 155

  Figure 42: Typical Overflux Current Waveform
  • 155

    Overfluxing Restraint
  • 156

    Figure 43: Phase Current Differential Protection Logic for Feeders With In-Zone Transformers
  • 157

    Figure 44: Second Harmonic Blocking Logic
  • 158

    Figure 45: Fifth Harmonic Blocking Logic
  • 159

    Figure 46: Permissive Intertripping Example
  • 159

    Current Differential Intertripping
  • 160

    Figure 47: Stub Bus Protection
  • 160

    Stub Bus Differential Protection
  • 161

    Application Notes
• 162

  Sensitivity Under Heavy Loads
• 163

  Permissive Intertripping
• 164

  Feeders With Small Tapped Loads
• 165

  Figure 48: Typical Two-Terminal Plain Feeder Circuit
• 165

  Setting a Three-Terminal Phase Current Differential Element
• 166

  Figure 49: Typical Three-Terminal Plain Feeder Circuit

169

Chapter 7 Distance Protection

• 171

  Chapter Overview
• 172

  Figure 50: System Impedance Ratio
• 172

  Introduction
• 173

  Impedance Calculation
• 174

  Distance Measuring Zones Operating Principles
• 175

  Figure 51: Directional Mho Element Construction
• 175

  Mho Characteristics
• 176

  Directional Self-Polarized Mho Characteristic for Earth Faults
• 176

  Figure 52: Offset Mho Characteristic
• 177

  Figure 53: Directional Mho Element Construction - Impedance Domain
• 178

  Figure 54: Offset Mho Characteristics - Impedance Domain
• 178

  Offset Mho Characteristic for Earth Faults
• 179

  Figure 55: Offset Mho Characteristics - Voltage Domain
• 180

  Figure 56: Simplified Forward Fault
• 180

  Memory Polarization of Mho Characteristics
• 181

  Figure 57: Mho Expansion - Forward Fault
• 182

  Figure 58: Simplified Reverse Fault
• 183

  Cross Polarization of Mho Characteristics
• 183

  Figure 59: Mho Contraction - Reverse Fault
• 184

  Implementation of Mho Polarization
• 185

  Figure 60: Simplified Quadrilateral Characteristics
• 185

  Quadrilateral Characteristic
• 186

  Directional Quadrilaterals
• 186

  Figure 61: General Quadrilateral Characteristic Limits
• 187

  Figure 62: Directional Quadrilateral Characteristic
• 188

  Figure 63: Quadrilateral Characteristic Featuring 2 Directional Forward Zones and 1 Offset Zone
• 189

  Figure 64: Five-Sided Polygon Formed By Quadrilateral Characteristic With Directional-Line
• 190

  Earth Fault Quadrilateral Characteristics
• 192

  Figure 65: Impedance Reach Line in Z1 Plane
• 193

  Figure 66: Impedance Reach Line in ZLP Plane
• 194

  Figure 67: General Characteristic in ZLP Plane
• 195

  Figure 68: Phase Relations Between I2 and Iph for Leading and Lagging Polarizing Currents
• 196

  Figure 69: General Characteristic in Z1 Plane
• 197

  Figure 70: Simplified Characteristic in Z1 Plane
• 198

  Quadrilateral Characteristic for Phase Faults
• 199

  Figure 71: Impedance Reach Line Construction
• 199

  Phase Fault Impedance Reach Line
• 200

  Figure 72: Reverse Impedance Reach Line Construction
• 200

  Figure 73: Resistive Reach of Phase Elements
• 200

  Phase Fault Resistive Reach Line
• 201

  Figure 74: Resistive Reach Line Construction
• 202

  Figure 75: Reverse Resistive Reach Line Construction
• 202

  Figure 76: Phase Fault Quadrilateral Characteristic Summary
• 202

  Phase Fault Reverse Resistive Reach Line
• 204

  Phase and Earth Fault Distance Protection Implementation
• 205

  Distance Protection Phase Selection
• 206

  Biased Neutral Current Detector
• 206

  Figure 77: Phase to Phase Current Changes for C Phase-To-Ground (CN) Fault
• 207

  Distance Element Zone Settings
• 207

  Figure 78: Biased Neutral Current Detector Characteristic
• 208

  Advanced Distance Zone Settings
• 209

  Capacitor VT Applications
• 210

  Figure 79: Load Blinder Characteristics
  • 210

    Load Blinding
  • 211

    Cross Country Fault Protection
  • 212

    Delta Directional Element
  • 213

    Figure 80: Sequence Networks Connection for an Internal A-N Fault
  • 213

    Delta Directional Decision
  • 214

    Figure 81: - DV Forward and Reverse Tripping Regions
  • 215

    Figure 82: Current Level (Amps) at Which Transient Faults Are Self-Extinguishing
  • 215

    Distance Isolated and Compensated Systems
  • 216

    Figure 83: Earth Fault in Petersen Coil Earthed System
  • 216

    Figure 84: Distribution of Currents During a Phase C Fault
  • 217

    Figure 85: Phasors for a Phase C Earth Fault in a Petersen Coil Earthed System
  • 217

    Figure 86: Zero Sequence Network Showing Residual Currents
  • 218

    Figure 87: Phase C Earth Fault in Petersen Coil Earthed System: Practical Case With Resistance
  • 218

    Earth Fault Distance Protection for Isolated and Compensated Systems
  • 219

    Single-Phase to Earth Faults On Isolated or Compensated Systems
  • 220

    Implementation of Distance Protection for Isolated and Compensated Networks
  • 221

    Figure 88: Voltage Distribution in an Isolated System for a Phase-A-To-Earth Fault
  • 221

    Figure 89: Biased Neutral Current Detector
  • 222

    Figure 90: First Earth Fault Detection
  • 222

    Fault Detection Logic
  • 223

    Figure 91: Second Earth Fault Detection Logic
  • 223

    Phase Preferential Logic
  • 225

    Figure 92: Priority Setting Enable Logic
  • 226

    Figure 93: Zone Starting Logic
  • 227

    Figure 94: Zone Timer Logic
  • 228

    Figure 95: Zone Trip Logic
  • 229

    Figure 96: Settings Required to Apply a Quadrilateral Zone
  • 229

    Application Notes
  • 230

    Figure 97: Settings Required to Apply a Mho Zone
  • 230

    Earth Fault Characteristic
  • 231

    Quadrilateral Resistive Reaches
  • 232

    Figure 98: Over-Tilting Effect
  • 232

    Dynamic Tilting
  • 233

    Fixed Tilting
    • 234

      Directional Element for Distance Protection
    • 235

      Load Blinding Setup
  • 236

    Delta Directional Element Setting Guidelines
  • 237

    Figure 99: Example Power System
  • 237

    Distance Protection Worked Example
• 238

  Line Impedance Calculation
• 239

  Zone 2 Phase and Ground Reach Settings
• 240

  Load Avoidance
• 242

  Figure 100: Apparent Impedances Seen By Distance Protection On a Teed Feeder
• 242

  Teed Feeder Applications

243

Chapter 8 Carrier Aided Schemes

• 245

  Chapter Overview
• 246

  Introduction
• 247

  Figure 101: Scheme Assignment
  • 247

    Carrier Aided Schemes Implementation
  • 248

    Default Carrier Aided Schemes
  • 249

    Aided Distance Scheme Logic
  • 250

    Figure 102: Aided Distance PUR Scheme
  • 250

    Permissive Over-Reach Scheme
  • 252

    Figure 103: Aided Distance POR Scheme
  • 252

    Permissive Overreach Trip Reinforcement
  • 253

    Permissive Overreach Weak Infeed Features
  • 254

    Figure 104: Example of Fault Current Reversal of Direction
• 254

  Current Reversal Guard Logic
• 255

  Aided Distance Blocking Schemes
• 256

  Aided Distance Unblocking Schemes
• 256

  Figure 105: Aided Distance Blocking Scheme (BOP)
• 258

  Figure 106: Aided Distance Send Logic
• 259

  Figure 107: Carrier Aided Schemes Receive Logic
• 259

  Figure 108: Aided Distance Tripping Logic
• 260

  Figure 109: PUR Aided Tripping Logic
• 261

  Figure 110: POR Aided Tripping Logic
• 262

  Figure 111: Aided Scheme Blocking 1 Tripping Logic
• 262

  Figure 112: Aided Scheme Blocking 2 Tripping Logic
• 263

  Aided DEF Scheme Logic
• 264

  Zero Sequence Polarizing
• 265

  Figure 113: Virtual Current Polarization
• 265

  Negative Sequence Polarizing
• 266

  Aided DEF Setting Guidelines
• 266

  Figure 114: Directional Criteria for Residual Voltage Polarization
• 267

  Aided DEF POR Scheme
• 268

  Figure 115: Aided DEF POR Scheme
• 269

  Aided DEF Logic Diagrams
• 269

  Figure 116: Aided DEF Blocking Scheme
• 269

  Figure 117: DEF Directional Signals
• 270

  Figure 118: Aided DEF Send Logic
• 270

  Figure 119: Carrier Aided Schemes Receive Logic
• 271

  Figure 120: Aided DEF Tripping Logic
• 272

  Figure 121: POR Aided Tripping Logic
• 273

  Figure 122: Aided Scheme Blocking 1 Tripping Logic
• 273

  Figure 123: Aided Scheme Blocking 2 Tripping Logic
• 274

  Aided Delta Scheme Logic
• 275

  Figure 124: Aided Delta POR Scheme
• 276

  Figure 125: Aided Delta Blocking Scheme
• 277

  Figure 126: Aided Delta Send Logic
• 277

  Figure 127: Carrier Aided Schemes Receive Logic
• 278

  Figure 128: Aided Delta Tripping Logic
• 279

  Figure 129: POR Aided Tripping Logic
• 280

  Figure 130: Aided Scheme Blocking 1 Tripping Logic
• 280

  Figure 131: Aided Scheme Blocking 2 Tripping Logic
  • 281

    Application Notes
• 282

  Aided DEF POR Scheme
• 283

  Figure 132: Apparent Impedances Seen By Distance Protection On a Teed Feeder
  • 283

    Teed Feeder Applications
• 284

  POR Schemes for Teed Feeders
• 285

  Blocking Schemes for Teed Feeders

287

Chapter 9 Non-Aided Schemes

• 285

  Figure 133: Problematic Fault Scenarios for PUR Scheme Application to Teed Feeders