Memory Expansion Port (Port A); On-Chip Emulator (Once); Phase-Locked Loop (Pll) Based Clocking; Section 2.7 Memory Expansion Port (Port A) - Motorola DSP56000 Manual

rectly addressable registers: the program counter (PC), loop address (LA), loop counter
(LC), status register (SR), operating mode register (OMR), and stack pointer (SP). The
16-bit PC can address 65,536 locations in program memory space.
There are four mode and interrupt control pins that provide input to the program interrupt
controller. The Mode Select A/External Interrupt Request A(MODA/IRQA) and Mode Se-
lect B/External Interrupt Request B (MODB/IRQB) pins select the chip operating mode
and receive interrupt requests from external sources.
The Mode Select C/Non-Maskable Interrupt (MODC/NMI) pin provides further operating
mode options and non-maskable interrupt input.
The RESET pin resets the chip. When it is asserted, it initializes the chip and places it in
the reset state. When it is deasserted, the chip assumes the operating mode indicated by
the MODA, MODB, and MODC pins.
2.7

MEMORY EXPANSION PORT (PORT A)

Port A synchronously interfaces with a wide variety of memory and peripheral devices
over a common 24-bit data bus. These devices include high-speed static RAMs, slower
memory devices, and other DSPs and MPUs in master/slave configurations. This variety
is possible because the expansion bus timing is programmable and can be tailored to
match the speed requirements of the different memory spaces. Not all DSP56K family
members feature a memory expansion port. See the individual device's User's Manual to
determine if a particular chip includes this feature.
2.8

ON-CHIP EMULATOR (OnCE)

DSP56K on-chip emulation (OnCE) circuitry allows the user to interact with the DSP56K
and its peripherals non-intrusively to examine registers, memory, or on-chip peripherals.
It provides simple, inexpensive, and speed independent access to the internal registers
for sophisticated debugging and economical system development.
Dedicated OnCE pins allow the user to insert the DSP into its target system and retain
debug control without sacrificing other user accessible on-chip resources. The design
eliminates the costly cabling and the access to processor pins required by traditional em-
ulator systems.
2.9

PHASE-LOCKED LOOP (PLL) BASED CLOCKING

The PLL allows the DSP to use almost any available external system clock for full-speed
operation, while also supplying an output clock synchronized to a synthesized internal
clock. The PLL performs frequency multiplication, skew elimination, and low-power
division.
2- 6 DSP56K CENTRAL ARCHITECTURE OVERVIEW
MEMORY EXPANSION PORT (PORT A)
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