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2 POWER SUPPLY, RESET, AND CLOCKS
CLGSCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
CLG Oscillation Control Register
Register name
Bit
CLGOSC
15–12 –
11
10
9
8
7–4 –
3
2
1
0
Bits 15–12 Reserved
Bit 11
EXOSCSLPC
Bit 10
OSC3SLPC
Bit 9
OSC1SLPC
Bit 8
IOSCSLPC
These bits control the clock source operations in SLEEP mode.
1 (R/W): Stop clock source in SLEEP mode
0 (R/W): Continue operation state before SLEEP
Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCSLPC bit: EXOSC clock input
CLGOSC.OSC3SLPC bit: OSC3 oscillator circuit
CLGOSC.OSC1SLPC bit: OSC1 oscillator circuit
CLGOSC.IOSCSLPC bit:
Bits 7–4
Reserved
Bit 3
EXOSCEN
Bit 2
OSC3EN
Bit 1
OSC1EN
Bit 0
IOSCEN
These bits control the clock source operation.
1(R/W):
Start oscillating or clock input
0(R/W):
Stop oscillating or clock input
Each bit corresponds to the clock source as follows:
CLGOSC.EXOSCEN bit: EXOSC clock input
CLGOSC.OSC3EN bit:
CLGOSC.OSC1EN bit:
CLGOSC.IOSCEN bit:
2-18
Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings
0x0
IOSCCLK
1/8
1/4
1/2
1/1
Bit name
Initial
0x0
EXOSCSLPC
OSC3SLPC
OSC1SLPC
IOSCSLPC
0x0
EXOSCEN
OSC3EN
OSC1EN
IOSCEN
IOSC oscillator circuit
OSC3 oscillator circuit
OSC1 oscillator circuit
IOSC oscillator circuit
Seiko Epson Corporation
CLGSCLK.CLKSRC[1:0] bits
0x1
0x2
OSC1CLK
OSC3CLK
1/16
Reserved
1/8
Reserved
1/2
1/2
1/1
1/1
Reset
R/W
–
R
–
1
H0
R/W
1
H0
R/W
1
H0
R/W
1
H0
R/W
–
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
1
H0
R/W
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
Remarks
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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