Clock Generator (Clg); Overview - Epson S1C17W18 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS

2.3 Clock Generator (CLG)

2.3.1 Overview

CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral
circuits. The main features of CLG are outlined below.
• Supports multiple clock sources.
- IOSC oscillator circuit that oscillates with a fast startup and no external parts required
- High-precision and low-power OSC1 oscillator circuit that uses a 32.768 kHz crystal resonator
- OSC3 oscillator circuit in which the oscillator type can be specified from crystal/ceramic oscillator (an exter-
nal resonator is required), CR oscillator (an external R is required), and internal oscillator
- EXOSC clock input circuit that allows input of square wave and sine wave clock signals
• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the peripheral cir-
cuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.
• IOSCCLK output from the IOSC oscillator circuit is used as the boot clock for fast booting.
• Controls the oscillator and clock input circuits to enable/disable according to the operating mode, RUN or
SLEEP mode.
• Provides a flexible system clock switching function at SLEEP mode cancelation.
- The clock sources to be stopped in SLEEP mode can be selected.
- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation.
• Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal
state.
Figure 2.3.1.1 shows the CLG configuration.
CLG
OSC1
X'tal1
OSC2
OSC3
R X'tal3/Ceramic3
CR3
OSC4
EXOSC
FOUT
2-6
IOSCEN
IOSC
IOSCCLK
oscillator Divider
circuit
OSC1EN
OSC1
OSC1CLK
oscillator Divider
circuit
OSC3EN
OSC3
OSC3CLK
oscillator Divider
circuit
EXOSCEN
EXOSC
EXOSCCLK
clock input
circuit
FOUTEN
FOUT
output
circuit
FOUTDIV[2:0]
Figure 2.3.1.1 CLG Configuration
Seiko Epson Corporation
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
System
Clock
SYSCLK
clock
selector
controller
SLEEP, WAKE-UP
Clock
selector
Clock
selector
S1C17W18 TECHNICAL MANUAL
To CPU and bus
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
(Rev. 1.2)