Effects Of Errors On Slave Cpu Synchronization Operation - YASKAWA MP210 Series User Manual

Appendix F MP2100M Slave CPU Synchronization Function
F.4.2 Effects of Errors on Slave CPU Synchronization Operation
F.4.2 Effects of Errors on Slave CPU Synchronization Operation
The operation of the slave devices when errors occur during slave CPU synchronization are as follows.
Phenomenon/Procedure
Turning the master device power
OFF
MECHATROLINK communication
cable disconnection
Deletion of the MP2100M allocation
at the master device
Saving a MECHATROLINK defini-
tion at the master device
Occurrence of a transmission error
RUN/STOP of the CPU at the mas-
ter device
RUN/STOP of the CPU at slave de-
vices
Changing the high-speed scan set-
ting at the master device
Changing the high-speed scan set-
ting at a slave device
F-32
Operation is continued in the slave CPU asynchronous status.
An input error occurs, but there is no effect on other scan operations, etc.
Operation is continued in the slave CPU asynchronous status.
An input error occurs, but there is no effect on other scan operations, etc.
Operation is continued in the slave CPU asynchronous status.
An input error occurs, but there is no effect on other scan operations, etc.
The slave CPU asynchronous status is temporarily established.
If the status of control bit SLVSC is OFF, the slave CPU synchronous status is re-
established after the master device has been reset and communication has been
restarted.
If it is just a receive data error, there is no effect on slave CPU synchronization.
However, since the input data is not refreshed, if a check is performed in the user
application a scan counter error may be detected depending on the scan cycle and
communication cycle settings.
If an error of MECHATROLINK communication itself occurs (e.g. disruption of
the transmission cycle), slave CPU synchronization may be affected. In some
cases high-speed scan processing at the MP2100S could be disrupted.
CPU RUN/STOP operations have no effect on slave CPU synchronization.
CPU RUN/STOP operations have no effect on slave CPU synchronization.
The slave CPU asynchronous status is temporarily established.
Provided that the high-speed scan setting after the change satisfies the slave CPU
synchronization execution conditions and also that the control bit SLVSC is OFF,
the slave CPU synchronous status is re-established.
The slave CPU asynchronous status is temporarily established.
Provided that the high-speed scan setting after the change satisfies the slave CPU
synchronization execution conditions and also that the control bit SLVSC is OFF,
the slave CPU synchronous status is re-established.
Operation