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4.1 Confirming I/O Allocation
■
Allocation of I/O signals
Signal name
When using the
transistor output
Control Unit
When using the
relay output type
pulse I/O cassette
4.1.4 When Using High-speed Counter Function
● The following reserved areas are allocated to the hardware reset input or control active flag.
■
Allocation of I/O signals (When using internal input)
Signal name
Count input
Hardware reset
input
Control active flag
(BUSY)
■
Allocation of I/O signals (When using the input section of the pulse I/O cassette)
Signal name
Count input
Hardware reset
input
Control active flag
(BUSY)
(Note 1)
The input X102 can be set to either CH8 or CH9 and the input X202 can be set to either CHA or CHB
as a hardware reset input.
4-6
CH0
PWM output
Y0
Control active
R911C
flag (BUSY)
PWM output
Y100
Control active
R911C
flag (BUSY)
CH0
Single-phase
X0
input
2-phase input
X0 / X1
Single-phase
X6
input
2-phase input
X6
Single-phase
R9110
input
2-phase input
R9110
CH8
Single-phase
X100
input
2-phase input
X100 / X101
Single-phase
X102
input
2-phase input
X102
Single-phase
R9118
input
2-phase input
R9118
I/O No.
CH1
Y2
R911D
Y200
R911D
I/O No.
CH1
CH2
CH3
X1
X2
X3
-
X2 / X3
-
-
X7
-
-
X7
-
R9111
R9112
R9113
-
R9112
-
I/O No.
CH9
X101
-
X102
X102
R9119
-
CH2
Y4
R911E
R911F
-
-
CH4
CH5
CH6
X4
X5
X6
X4 / X5
-
X6 / X7
-
-
-
-
-
-
R9114
R9115
R9116
R9114
-
R9116
CHA
X200
X200 / X201
X202
X202
R911A
R911B
R911A
WUME-FPXHPOSG-01
CH3
Y6
-
-
CH7
X7
-
-
-
R9117
-
CHB
X201
-
X202
X202
-
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