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Code
Value
(a)
Upper limit
Target value 2: OFF
(b)
set value
Target value 2: ON set
(c)
value
Target value 1: OFF
(d)
set value
Target value 1: ON set
(e)
value
(1)
Execution condition
High-speed counter
instruction
(2)
active flag
(3)
Cam output
(4)
Interrupt
(5)
Reset signal
(Note 1)
It shows the hardware reset input (X2) for the high-speed counter CH0.
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Sample program
Code
Description
(1)
High-speed counter channel H10: Performs the upper limit control, CH0
(2)
Cam output device type K1: Internal relay (R)
(3)
Word number of cam output device K10
WUME-FPXHPOSG-01
10.4 High-speed Counter Cam Control Instruction
Description
When the elapsed value exceeds the upper limit, it returns to 0.
The cam output is performed according to the target values.
In this example, the ON set value is smaller than the OFF set value for each
target value.
Therefore, When added: When the elapsed value reaches the ON set value,
the cam output turns ON, and when it reaches the OFF set value, it turns
OFF.
When subtracted: When the elapsed value falls below the OFF set value, the
cam output turns ON, and when it falls below the ON set value, it turns OFF.
When the execution condition turns ON from OFF, the instruction is executed
and the cam control starts.
The high-speed counter instruction active flag turns ON during the execution
of the instruction. Even when the reset signal exists, the execution of the
nstruction continues.
The output turns ON/OFF according the set values.
When the elapsed value reaches the ON set value, the interrupt program
starts.
When the hardware reset (X2) or software reset DT90052 (bit 0) turns ON,
the elapsed value of the high-speed counter is rest to 0. The outputs
corresponding to the elapsed value 0 (both R100 and R101 in the above
example) become OFF.
10-25
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