Interrupt Setup Examples; Setting Up An External Pin Interrupt; Block Diagram Of External Pin Interrupt; Panasonic - Panasonic MN10285K User Manual

Panasonic Semiconductor Development Company
2.2

Interrupt Setup Examples

2.2.1

Setting Up an External Pin Interrupt

In this example, an interrupt occurs on a falling-edge signal from the IRQ0 (P00)
external interrupt pin, and the interrupt priority level is 5.
On reset, the external edge setting in the EXTMD register is low (b'00' = active-
low interrupt), and the IQ0IR bit of the IQ0ICL register is 0.
P5
IRQ0 P0
P2
Figure 2-4 Block Diagram of External Pin Interrupt
Enabling external interrupt 0
1. Set the interrupt conditions for the IRQ0 (P00) pin. For this example, set the
IQ0TG[1:0] bits of EXTMD to b'10' (negative-edge-triggered interrupt).
EXTMD (example)
Bit: 15 14 13 12
IQ5TG
0 0 0 0
Setting: — — — —
2. Cancel any existing interrupt requests and enable IRQ0 interrupts. To do
this, set the IQ0IR bit of IQ0ICL to 0, set the IQ0LV[2:0] bits of IQ0ICH to
b'101' (priority level 5), and set the IQ0IE bit to 1.
IQ0ICL (example)
Bit: 7 6 5 4
— — — IQ0IR
Setting: 0 0 0 0
IQ0ICH (example)
Bit: 7 6 5 4
— IQ0LV2 IQ0LV1 IQ0LV0
Setting: 0 1 0 1
40

Panasonic

CORE
Interrupts
Timers 0-5
11 10 9 8
7 6
IQ5TG IQ4TG IQ4TG IQ3TG IQ3TG
1 0 1 0 1 0
0 0 0 0 0 0
3 2 1 0
— — — IQ0ID
0 0 0 0
3 2 1 0
— — — IQ0IE
0 0 0 1
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
Interrupt Setup Examples
ROM, RAM
P1
Bus Controller
P3
Serial I/Fs
ADC
x'00FCF8'
5 4 3 2 1
IQ2TG IQ2TG IQ1TG IQ1TG IQ0TG IQ0TG
1 0 1 0 1
0 0 0 0 1
x'00FC48'
x'00FC49'
0
0
0