Panasonic MN10285K User Manual page 116

Timers
16-Bit Timer Setup Examples
Use the MOV instruction for this
setup and only use 16-bit write
operations.
This step stops the TM5BC
count and clears both TM5BC
and the S-R flip-flop to 0.
MN102H75K/F75K/85K/F85K LSI User Manual
To set up timer 5:
1. Set the operating mode in the timer 5 mode register (TM5MD). Disable timer
5 counting and interrupts. The up/down count bit is ignored in this instance.
Set the TM5NLP bit to 1 to select looped counting from 0 to the value in
TM5CA. Select the 1x two-phase encoder as the clock source.
TM5MD (example)
Bit: 15 14 13 12
TM5 TM5 TM5
— —
EN NLD UD1
Setting: 0 0 0 0
2. Write the intended looping value for timer 5 to TM5CA (valid settings:
x'0001' to x'FFFF'). For TM5BC to count from x'0000' to x'1FFF', for
instance, write x'1FFF' to TM5CA.
TM5CA (example)
Bit: 15 14 13 12
TM5 TM5 TM5 TM5 TM5
CA15 CA14 CA13 CA12 CA11
Setting: 0 0 0 1
3. Write the timer 5 interrupt value (valid settings: x'0000' to the value in
TM5CA) to TM5CB. Whenever the binary counter reaches the value in
TM5CB, in either up or down counting, a compare/capture B interrupt
occurs at the beginning of the next cycle.
TM5CB (example)
Bit: 15 14 13 12
TM5 TM5 TM5 TM5 TM5
CB15 CB14 CB13 CB12 CB11
Setting: 0 0 0 1
4. Set the TM5NLD bit of the TM5MD register to 1 and the TM5EN bit to 0.
This enables TM5BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not
change any other operating modes during this step.
5. Set TM5NLD and TM5EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
To enable timer 5 capture B interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM5CBLV[2:0] bits of the TM5CBICH register (levels 0 to 6), set the TM5BIE
bit to 1, and set the TM5BIR bit of TM5CBICL to 0. From this point on, an
interrupt request is generated whenever a timer 5 capture B event occurs.
115
Panasonic
11 10 9 8 7 6
TM5 TM5 TM5 TM5 TM5
UD0 TGE ONE MD1 MD0
0 0 0 0 0 0
11 10 9 8 7 6
TM5 TM5 TM5 TM5 TM5
CA10 CA9 CA8 CA7 CA6
1 1 1 1 1 1
11 10 9 8 7 6
TM5 TM5 TM5 TM5 TM5
CB10 CB9 CB8 CB7 CB6
0 0 0 0 0 0
Panasonic Semiconductor Development Company
x'00FE90'
5 4 3 2 1
TM5 TM5 TM5 TM5 TM5 TM5
ECLR LP ASEL S2 S1
0 1 1 or 0 1 0
x'00FE94'
5 4 3 2 1
TM5 TM5 TM5 TM5 TM5 TM5
CA5 CA4 CA3 CA2 CA1 CA0
1 1 1 1 1
x'00FE98'
5 4 3 2 1
TM5 TM5 TM5 TM5 TM5 TM5
CB5 CB4 CB3 CB2 CB1 CB0
0 0 0 0 0
0
S0
1
0
1
0
0