Panasonic MN10285K User Manual page 243

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DATAE: Data Capture Stop Timing Control Register
(DATAEW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
DATAE[10:0]: Stop position for data capture
Set this value high enough to allow the last data to be captured. The valid
range is x'000' to x'7FF'.
STAP: Sampling Start Position Register (Software Setting)
(STAPW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
SFTSTAP[10:0]: Software setting for sampling start position (in clock units)
FCPNUM: Sampling Start Position Register (Hardware Calculation)
(FCPNUMW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
FCPNUM[10:0]: Sampling start position calculated by the hardware
NFSEL: Noise Filter Select Register
(NFSELW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
This register selects the low-pass filter, which eliminates noise and high-
frequency signals that are unnecessary to the sync separator and the clamp-
ing controller. The recommended setting for NFSEL is x'0000'.
MING: Output select for noise filter detecting minimum sync tip
0: Low-pass filter 1
1: Low-pass filter 2, 3, or 4 (set in NFSW[1:0])
NFSW[1:0]: Noise filter switch (for composite sync separator)
00: Low-pass filter 3
01: Low-pass filter 4
10: Low-pass filter 2
11: Low-pass filter 1
The cutoff frequencies for low-pass filters 1 to 4 are lower in ascending
order, so that low-pass filter 4 eliminates the highest amount of noise.
242
Panasonic
Closed-Caption Decoder
Closed-Caption Decoder Registers
11 10 9 8 7 6
DATA DATA DATA DATA DATA
— E E E E E
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
11 10 9 8 7 6
SFT SFT SFT SFT SFT
— STAP STAP STAP STAP STAP
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
11 10 9 8 7 6
FCP FCP FCP FCP FCP
— NUM NUM NUM NUM NUM
10 9 8 7 6
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
— — — MING — —
0 0 0 0 0 0
R R R R/W R R
MN102H75K/F75K/85K/F85K LSI User Manual
x'007E1A'
x'007E3A')
5 4 3 2 1
DATA DATA DATA DATA DATA DATA
E E E E E
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
x'007E1C'
x'007E3C')
5 4 3 2 1
SFT SFT SFT SFT SFT SFT
STAP STAP STAP STAP STAP STAP
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
x'007E1E'
x'007E3E')
5 4 3 2 1
FCP FCP FCP FCP FCP FCP
NUM NUM NUM NUM NUM NUM
5 4 3 2 1
0 0 0 0 0
R R R R R
x'007EC0'
x'007EE0')
5 4 3 2 1
NFSW NFSW
— — — —
1
0 0 0 0 0
R R R R R/W R/W
0
E
0
1
0
0
1
0
0
0
R
0
0
0