Panasonic MN10285K User Manual page 247

Panasonic Semiconductor Development Company
HSEP1: HSYNC Separator Control Register 1
(HSEP1W
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
HSFREQ[10:0]: Correction HSYNC frequency
Set the correction HSYNC cycle in this field in HSYNC separator sam-
pling clock units. The valid range is x'000' to x'7FF', and the recom-
mended setting is x'010C'.
HSEP2: HSYNC Separator Control Register 2
(HSEP2E
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
HCLOSEE[9:0]: Start position for HSYNC detection
Set the position in HSYNC separator sampling clock units. The valid range
is x'000' to x'3FF', and the recommended setting is x'00E4'.
FIELD: Field Detection Control Register
(FIELDW
Bit: 15 14 13 12
ODD
— — —
EVEN
Reset: 0 0 0 0
R/W: R R R R
ODDEVEN: Field detection signal
0: Odd field
1: Even field
VPHASE[9:0]: Phase difference setting for VSYNC and HSYNC
Set the phase difference in HSYNC separator sampling clock units. The
valid range is x'000' to x'3FF'.
HLOCKLV: Sync Separator Detection Control Register 1
(HLOCKLVW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
HLOCKLV[8:0]: Sync separator detection threshold
This value is compared to the count of the corrected HSYNC. The valid
range is x'000' to x'1FF', and the recommended setting is x'0008'.
HLOCKLV HSYNC count
HLOCKLV HSYNC count
246
Panasonic
Closed-Caption Decoder
Closed-Caption Decoder Registers
11 10 9 8 7 6
HS HS HS HS HS
— FREQ FREQ FREQ FREQ FREQ
10 9 8 7 6
0 0 0 1 0 0
R R/W R/W R/W R/W R/W
11 10 9 8 7 6
H H H H
— — CLOSE CLOSE CLOSE CLOSE
E9 E8 E7 E6
0 0 0 0 1 1
R R R/W R/W R/W R/W
11 10 9 8 7 6
V V V V
— — PHASE PHASE PHASE PHASE
9 8 7 6
0 0 0 0 1 0
R R R/W R/W R/W R/W
11 10 9 8 7 6
H H H
— — — LOCK LOCK LOCK
LV8 LV7 LV6
0 0 0 0 0 0
R R R R/W R/W R/W
asynchronous
synchronous
MN102H75K/F75K/85K/F85K LSI User Manual
x'007ECE'
x'007EEE')
5 4 3 2 1
HS HS HS HS HS
FREQ FREQ FREQ FREQ FREQ FREQ
5 4 3 2 1
0 0 1 1 0
R/W R/W R/W R/W R/W R/W
x'007ED0'
x'007EF0')
5 4 3 2 1
H H H H H
CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE
E5 E4 E3 E2 E1
1 0 0 1 0
R/W R/W R/W R/W R/W R/W
x'007ED2'
x'007EF2')
5 4 3 2 1
V V V V V
PHASE PHASE PHASE PHASE PHASE PHASE
5 4 3 2 1
0 0 0 0 0
R/W R/W R/W R/W R/W R/W
x'007ED4'
x'007EF4')
5 4 3 2 1
H H H H H
LOCK LOCK LOCK LOCK LOCK LOCK
LV5 LV4 LV3 LV2 LV1 LV0
0 0 1 0 0
R/W R/W R/W R/W R/W R/W
0
HS
0
0
0
H
E0
0
0
V
0
0
0
H
0